Power efficiency of voltage scaling in multiple clock, multiple voltage cores

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 379-386

  Iyer, Anoop ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; MULTIPLE CLOCK DYNAMIC VOLTAGE; MULTIPLE CLOCK SINGLE VOLTAGE; POWER CONSUMPTION; SINGLE CLOCK DYNAMIC VOLTAGE;

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

TIMING CIRCUITS;

EID: 0036916955     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774629     Document Type: Conference Paper

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