Statistical static timing analysis: How simple can we get?

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 652-657

  Amin, Chirayu S ^a   Menezes, Noel ^b   Killpack, Kip ^b   Dartu, Florentin ^b   Choudhury, Umakanta ^b   Hakim, Nagib ^b   Ismail, Yehea I ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Process Variations; Statistical Static Timing Analysis (SSTA)

Indexed keywords

PARAMETER ESTIMATION; PERFORMANCE; STATISTICS;

CIRCUIT PERFORMANCE; PROCESS VARIATIONS;

PROCESS ENGINEERING;

EID: 27944448528     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193892     Document Type: Conference Paper

References (17)

1. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single Pert-like traversal," ICCAD'03, pp. 621-625.
2. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," DAC'04, pp. 331-336.
3. J. A. G. Jess et. al., "Statistical timing for parametric yield prediction of digital integrated circuits," DAC'03, pp. 932-937.
4. A. Devgan and C. Kashyap, "Block-based static timing analysis with uncertainty," ICCAD'03, pp. 607-614.
5. M. Orshansky and A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," DAC'04, pp. 337-342.
6. M. Orshansky and K. Keutzer, "A general probabilistic framework for worst case timing analysis," DAC'02, pp. 556-561.
7. A. Agarwal, V. Zolotov, and D. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE Trans. on CAD, vol. 22, no. 9, pp. 1243-1260, September 2003.
8. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," ICCAD'03, pp. 900-907.
9. F. N. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," DAC'04, pp. 460-465.
10. A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation from static timing analysis," ISQED'01, pp. 437-442.
11. S. Nassif, "Delay variability: sources, impact and trends," ISSCC'00, pp. 368-369.
12. A. Papoulis and S. U. Pillai, Probability, Random Variables, and Stochastic Processes, fourth edition, McGraw Hill, 2002.
13. J. K. Ousterhout, "A switch-level timing verifier for Digital MOS VLSI," IEEE Trans. on CAD, vol. 4, no. 3, pp. 336-349, July 1985.
14. N. P. Jouppi, "Timing analysis and performance improvement of MOS VLSI Designs," IEEE Trans. on CAD, vol. CAD-6, no. 4, pp. 650-665, July 1987.
15. International Technology Roadmap for Semiconductors (ITRS), 2003 edition, Semiconductor Industry Association (http://public.itrs.net/).
16. T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas," IEEE JSSC, vol. 25, no. 2, pp. 584-594, April 1990.
17. S. Samaan, "The Impact of Device Parameter Variations on the Frequency and Performance of VLSI Chips," ICCAD'04. (Also published in ISSCC'04.)