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Volumn 13, Issue 3, 1998, Pages 315-319

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Author keywords

Cell fault model (CFM); Fault simulation; Stuck at fault model; Test pattern generation

Indexed keywords

AUTOMATIC TESTING; COMPUTER SIMULATION; EQUIVALENT CIRCUITS;

EID: 0032303527     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008389920806     Document Type: Article
Times cited : (14)

References (10)
  • 2
    • 0028750501 scopus 로고
    • A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
    • Dec.
    • A.D. Friedman, "A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays," IEEE Trans. on Computers, Vol. 43, No. 12, pp. 1365-1375, Dec. 1994.
    • (1994) IEEE Trans. on Computers , vol.43 , Issue.12 , pp. 1365-1375
    • Friedman, A.D.1
  • 3
    • 0029547379 scopus 로고
    • An Effective BIST Scheme for Carry-Save and Carry Propagate Array Multipliers
    • Nov.
    • D. Gizopoulos, A. Paschalis, and Y. Zorian, "An Effective BIST Scheme for Carry-Save and Carry Propagate Array Multipliers," Proc. 4th IEEE Asian Test Symposium, Nov. 1995, pp. 286-292.
    • (1995) Proc. 4th IEEE Asian Test Symposium , pp. 286-292
    • Gizopoulos, D.1    Paschalis, A.2    Zorian, Y.3
  • 8
    • 0029516849 scopus 로고
    • Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests
    • M. Gharaybeh, M. Bushnell, and V. Agrawal, "Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests," Proc. IEEE Int. Test Conf., 1995, pp. 139-148.
    • (1995) Proc. IEEE Int. Test Conf. , pp. 139-148
    • Gharaybeh, M.1    Bushnell, M.2    Agrawal, V.3
  • 9
    • 0020550192 scopus 로고
    • Test Generation for MOS Circuit Using D-Algorithm
    • S.K. Jain and V.D. Agrawal, "Test Generation for MOS Circuit Using D-Algorithm," Proc. DAC, 1983, pp. 64-70.
    • (1983) Proc. DAC , pp. 64-70
    • Jain, S.K.1    Agrawal, V.D.2
  • 10
    • 0021156744 scopus 로고
    • A Gate-Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection
    • S.M. Reddy, V.D. Agrawal, and S.K. Jain, "A Gate-Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection," Proc. DAC, 1984, pp. 504-509.
    • (1984) Proc. DAC , pp. 504-509
    • Reddy, S.M.1    Agrawal, V.D.2    Jain, S.K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.