Delay fault testing of designs with embedded IP cores

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 160-167

  Kim, Hyungwon ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

DELAY FAULT TESTING METHODS; INTELLECTUAL PROPERTY CIRCUIT; SELECTIVELY TRANSPARENT SCAN;

INTEGRATED CIRCUIT TESTING;

EID: 0032655689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (16)