Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

IEEE Transactions on Computers

Volumn 49, Issue 10, 2000, Pages 1083-1099

  Psarakis, Mihalis ^b   Gizopoulos, Dimitris ^a,c   Paschalis, Antonis ^a,d   Zorian, Yervant ^a,e  

^a IEEE

^b INSTITUTE OF INFORMATICS AND TELECOMMUNICATIONS   (Greece)

^c UNIVERSITY OF PIRAEUS   (Greece)

^d UNIVERSITY OF ATHENS   (Greece)

^e LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; LOGIC DESIGN; MATHEMATICAL MODELS; VLSI CIRCUITS;

AUTOMATIC TEST PATTERN GENERATOR; GRAPH MODEL; ITERATIVE LOGIC ARRAYS; REALISTIC SEQUENTIAL CELL FAULT MODEL; SEQUENTIAL FAULT MODELING; TEST PATTERN GENERATION;

LOGIC CIRCUITS;

EID: 0034291645     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.888044     Document Type: Article

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