A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 53-58

  Dervisoglu, B I ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIERARCHICAL SYSTEMS; INTELLECTUAL PROPERTY; SHIFT REGISTERS; STANDARDS;

SYSTEM ON A CHIP (SOC);

CHIP SCALE PACKAGES;

EID: 0034846647     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378280     Document Type: Conference Paper

References (10)

1. Shared I/O-cell structures: A framework for extending the IEEE 1149.1 boundary-scan standard
2. An architecture for extending the IEEE standard 1149.1 test access port to system backplanes
3. Towards a standard for embedded core test: An example
4. Status and summary of IEEE P1149.2
5. Shared I/O-cell structures: A framework for extending the IEEE 1149.1 boundary-scan standard
6. A novel approach for designing a hierarchical test access controller for embedded core designs in an SoC environment