Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2003-January, Issue , 2003, Pages 226-232

  Mishra, P ^a   Kejariwal, A ^a   Dutt, N ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architecture description languages; Clocks; Computer architecture; Embedded system; Frequency; Power generation; Power system modeling; Software performance; Software tools; System performance

Indexed keywords

ABSTRACTING; CLOCKS; COMPUTATIONAL LINGUISTICS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; MODELING LANGUAGES; PIPELINE PROCESSING SYSTEMS; POWER GENERATION; SPECIFICATIONS; SYSTEMS ANALYSIS;

ARCHITECTURE DESCRIPTION LANGUAGES; FREQUENCY; POWER SYSTEM MODEL; SOFTWARE PERFORMANCE; SYSTEM PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 84941269625     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWRSP.2003.1207052     Document Type: Conference Paper

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