Code size reduction in heterogeneous-connectivity-based DSPs using instruction set extensions

IEEE Transactions on Computers

Volumn 54, Issue 10, 2005, Pages 1216-1226

  Biswas, Partha ^a   Dutt, Nikil D ^a  

^a 5226 Donald Bren Hall   (United States)

Author keywords

ASIP; Code size reduction; Coprocessors; DSP; Instruction set extensions; VLIW

Indexed keywords

ALGORITHMS; HEURISTIC PROGRAMMING; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS (ASIP); CODE SIZE REDUCTION; COPROCESSORS; INSTRUCTION SET EXTENSIONS;

DIGITAL SIGNAL PROCESSING;

EID: 27444437658     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.157     Document Type: Article

References (23)

1. TI TMS320C6xx User Manual, http://www.ti.com, 2005.
2. Intel Itanium Processor, http://developer.intel.com/design/itanium/ manuals.htm, 2005.
3. S. Hanono and S. Devadas, "Instruction Selection, Resource Allocation and Scheduling in the AVIV Retargetable Code Generator," Proc. Design Automation Conf., pp. 510-515, 1998.
4. T.M. Conte, S. Banerjia, S.Y. Larin, K.N. Menezes, and S.W. Sathaye, "Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings," Proc. 29th Int'l Symp. Microarchitecture, pp. 201-211, 1996.
5. S. Aditya, S.A. Mahlke, and B.R. Rau, "Code Size Minimization and Retargetable Assembly for EPIC and VLIW Instruction Formats," Technical Report PL-2000-141, HP Labs, 2000.
6. M. Kozuch and A. Wolfe, "Compression of Embedded System Programs," Proc. Int'l Conf. Computer Design, pp. 270-277, 1994.
7. S.Y. Liao, S. Devadas, and K. Keutzer, "Code Density Optimization for Embedded DSP Processors using Data Compression Techniques," IEEE Trans. Computer Aided Design, vol. 17, no. 7, pp. 601-608, 1998.
8. H. Zhou and T.M. Conte, "Code Size Efficiency in Global Scheduling for ILP Processors," Proc Sixth Ann. Workshop Interaction between Compilers and Computer Architectures, 2002.
9. I.-J. Huang and A.M. Despain, "Generating Instruction Sets and Microarchitectures from Applications," Proc. Int'l Conf. Computer-Aided Design, 1994.
10. B.K. Holmer, "A Tool for Processor Instruction Set Design," Proc. Conf. European Design Automation, 1994.
11. J.-E. Lee, K. Choi, and N. Dutt, "Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs," Proc. Int'l Conf. Computer Aided Design, 2002.
12. H. Choi, J.-S. Kim, C.-W. Yoon, I.-C. Park, S.H. Hwang, and C.-M. Kyung, "Synthesis of Application Specific Instructions for Embedded DSP Software," IEEE Trans. Computers, 1999.
13. R. Leupers and P. Marwedel, "Instruction Selection for Embedded DSPs with Complex Instructions," Proc. European Design Automation Conf., 1996.
14. F. Onion, A. Nicolau, and N. Dutt, "Compiler Feedback in ASIP Design," Proc. Conf. Design, Automation, and Test in Europe, 1995.
15. M. Arnold and H. Corporaal, "Instruction Set Synthesis Using Operation Pattern Detection," Proc. Fifth Ann. Conf. Advanced School for Computing and Imaging, 1999.
16. F. Sun, S. Ravi, A. Raghunathan, and N.K. Jha, "Synthesis of Custom Processors Based on Extensible Platforms," Proc. Int'l Conf. Computer Aided Design, 2002.
17. D. Goodwin and D. Petkov, "Automatic Generation of Application Specific Processors," Proc. Int'l Conf. Compilers, Architectures, and Synthesis for Embedded Systems, 2003.
18. K. Atasu, L. Pozzi, and P. Ienne, "Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints," Proc. Design Automation Conf., 2003.
19. P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne, "ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement," Proc. Design, Automation and Test in Europe, 2005.
20. R.M. Karp, "Reducibility Among Combinatorial Problems," Complexity of Computer Computations, Plenum Press, 1972.
21. S.S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
22. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, "EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability," Proc. Conf. Design, Automation and Test in Europe, 1999.
23. M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, "MiBench: A Free Commercially Representative Embedded Benchmark Suite," Proc. IEEE Sixth Ann. Workshop Workload Characterization, http://www.eecs.umich.edu/jringenb/mibench/, Dec. 2001.