ISEGEN: Generation of high-quality instruction set extensions by iterative improvement

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1246-1251

  Biswas, Partha ^a   Banerjee, Sudarshan ^a   Dutt, Nikil ^a   Pozzi, Laura ^b   Ienne, Paolo ^b  

^a Ringgold Standard Institution Informatics   (United States)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; DATA FLOW ANALYSIS; HEURISTIC METHODS; ITERATIVE METHODS; SYSTEMS ANALYSIS;

CRYPTOGRAPHIC APPLICATION; INSTRUCTION SET EXTENSIONS (ISE);

EMBEDDED SYSTEMS;

EID: 33646927796     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.191     Document Type: Conference Paper

References (12)

1. F. Vahid and T. D. Le. Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning. In Kluwer Journal on Design Automation of Embedded Systems, 1997.
2. C. M. Fiduceia and R. M. Mattheyses. A Linear-time Heuristic for Improving Network Partitions, In Proc. of DAC, 1982.
3. K. Atasu, L. Pozzi and P. Ienne, Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In Proc. of DAC, 2003.
4. P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne and N. Dutt. Introduction of Local Memory Elements in Instruction Set Extensions. In Proc. of DAC. 2004.
5. N. Clark, H. Zhong and S. Mahlke, Processor Acceleration through Automated Instruction Set Customization. In Proc. of MICRO, 2003.
6. P. Yu and T. Mitra. Scalable Custom Instructions Identification for Instruction-Set Extensible Processors. In Proc. of CASES, 2004.
7. F. Sun, S. Ravi, A. Raghunathan and N. K. Jha. Synthesis of Custom Processors based on Extensible Platforms, In Proc. of ICCAD, 2002.
8. M. Arnold and H. Corporaal. Designing Domain-specific Processors. In Proc. of CODES, 2001.
9. P. Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne. ISEGEN: Adapting Kernighan-Lin Min-Cut Heuristic for Generation of Instruction Set Extensions. CECS, UC Irvine, Technical Report CECS-TR-04-21.
10. C. Alippi, W. Fornaciari, L. Pozzi and M. Sami. A DAG based Design Approach for Reconfigurable VLIW Processors. In Proc. of DATE, 1999.
11. R. Razdan and M. D. Smith. A High-performance Microarchitecture with Hardware-programmable Functional Units. In Proc. of MICRO, 1944.
12. Machine SUIF. http://www.eecs.harvard.edu/hube/software/software.html.