Code size efficiency in global scheduling for ILP processors

Proceedings - Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT

Volumn 2002-January, Issue , 2002, Pages 69-80

  Zhou, Huiyang ^a   Conte, T M ^a  

^a North Carolina State University   (United States)

Author keywords

Electronic switching systems; Processor scheduling; Read only memory; Robustness; Size measurement; Tail; Time measurement

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; EFFICIENCY; PROGRAM COMPILERS; ROBUSTNESS (CONTROL SYSTEMS); ROM; SCHEDULING; TIME MEASUREMENT;

CACHE PERFORMANCE; ELECTRONIC SWITCHING SYSTEMS; OPTIMAL EFFICIENCY; PROCESSOR SCHEDULING; QUANTITATIVE MEASURES; SIZE MEASUREMENTS; TAIL; THRESHOLD SCHEMES;

OPTIMAL SYSTEMS;

EID: 84948463556     PISSN: 15506207     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/INTERA.2002.995845     Document Type: Conference Paper

References (21)

1. th International Symposium on High-Performance Computer Architecture (HPCA-4), February 1998.
2. th Annual Workshop on Languages and Compilers for Parallel Computing (LCPC'01), LNCS, Springer Verlag, August 2001.
3. W. Y. Chen, P. P. Chang, T. M. Conte, and W. W. Hwu, "The Effect of Code Expanding Optimizations on Instruction Cache Design", Technical Report CRHC-91-17, University of Illinois, Urbana, May 1991
4. M. Jennings, H. Zhou, and T. M. Conte. "A Treegion-based Unified Approach to Speculation and Predication in Global Instruction Scheduling". Technical Report, ECE Department, NC State University, August 2001.
5. W.W. Hwu, S.A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery. "The Superblock: An effective way for VLIW and superblock compilation." The Journal of Supercomputing, vol. 7, pp. 229-248, January 1993.
6. V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1." Tech. Rep. HPL-93-80 (R.1), Hewlett - Packard Laboratories, February 2000.
7. th Ann. Int'l Symp. Microarchitecture (MICRO25), December 1992.
8. S. Aditya, V. Kathail, and B. R. Rau, "Elcor's machine description system: version 3.0." Tech. Rep. HPL-98-128 (R.1), Hewlett - Packard Laboratories, October 1998.
9. M. S. Schlansker and B. R. Rau. "EPIC: An architecture for instruction-level parallel processors" Tech. Rep. HPL-99-111, Hewlett - Packard Laboratories, February 2000.
10. th Int'l Symp. On Computer Architecture (ISCA18), 1991.
11. The LEGO Compiler. Available for download at http://www.tinker.ncsu.edu/LEGO.
12. F. Mueller and D. B. Whalley, "Avoiding Conditional Branches via Code Replication", ACM SIGPLAN Conference on Programming Language Design and Implementation, Jun 1995.
13. th Ann. Int'l Symp. Microarchitecture (MICRO24), 1991.
14. Bill Mangione-Smith, "Performance Bounds for Rapid Computer System Evaluation", in Fast Simulation of Computer Architectures, edited by Thomas M. Conte and Charles E. Gimarc, Kluwer Academic Publishers, 1995.
15. Intel Corp, IA-64 Application Developer's Architecture Guide, 2000.
16. B. R. Rau, "Iterative Module Scheduling", Tech. Rep. HPL-94-115, Hewlett - Packard Laboratories, 1995.
17. nd Ann. Int'l Symp. Microarchitecture (MICRO32), 1999.
18. Rainer Leupers, "Code Optimization Techniques for Embedded Processors", Kluwer Academic Publishers, 2000.
19. th Ann. Int'l Symp. Microarchitecture (MICRO29), December, 1996
20. J. Hoogerbrugge. "Dynamic branch prediction for a VLIW processor." Proc. Of the 2000 Conf. On Parallel Architectures and Compilation Techniques (PACT'00), October 1997.
21. H. Zhou and T. Conte. "Code Size Efficiency in Global Scheduling". Technical Report, ECE Department, NC State University, January 2002.