-
1
-
-
0003705271
-
An introduction to asynchronous circuit design
-
Univ. of Utah, Salt Lake City, Tech. Rep. UUCS-97-013 Sep.
-
A. Davis and S. M. Nowick, “An introduction to asynchronous circuit design,” Comp. Sci. Dep., Univ. of Utah, Salt Lake City, Tech. Rep. UUCS-97-013, Sep. 1997.
-
(1997)
Comp. Sci. Dep.
-
-
Davis, A.1
Nowick, S.M.2
-
2
-
-
0029191713
-
Asynchronous design methodologies: an overview
-
Jan.
-
S. Hauck, “Asynchronous design methodologies: an overview,” Proc. IEEE, vol. 83, no. 1, pp. 69–93, Jan. 1995.
-
(1995)
Proc. IEEE
, vol.83
, Issue.1
, pp. 69-93
-
-
Hauck, S.1
-
4
-
-
0033079595
-
Scanning the technology: applications of asynchronous circuits
-
Feb.
-
S. M. Nowick, K. van Berkel, and M. B. Josephs, “Scanning the technology: applications of asynchronous circuits,” Proc. IEEE, vol. 87, no. 2, pp. 223–233, Feb. 1999.
-
(1999)
Proc. IEEE
, vol.87
, Issue.2
, pp. 223-233
-
-
Nowick, S.M.1
van Berkel, K.2
Josephs, M.B.3
-
5
-
-
0036168734
-
Validating the AMULET microprocessors
-
S. B. Furber, “Validating the AMULET microprocessors,” Comp. J., vol. 45, no. 1, pp. 19–26, 2002.
-
(2002)
Comp. J.
, vol.45
, Issue.1
, pp. 19-26
-
-
Furber, S.B.1
-
6
-
-
77957932361
-
FLEETzero: an asynchronous switching experiment
-
W. S. Coates, J. K. Lexau, I. W. Jones, S. M. Fairbanks, and I. E. Sutherland, “FLEETzero: an asynchronous switching experiment,” in Proc. ASYNC'01, 2001, pp. 173–182.
-
(2001)
Proc. ASYNC'01
, pp. 173-182
-
-
Coates, W.S.1
Lexau, J.K.2
Jones, I.W.3
Fairbanks, S.M.4
Sutherland, I.E.5
-
7
-
-
0034431019
-
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
-
S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins, “Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz,” in Proc. ISSCC'00, pp. 292–293.
-
Proc. ISSCC'00
, pp. 292-293
-
-
Schuster, S.1
Reohr, W.2
Cook, P.3
Heidel, D.4
Immediato, M.5
Jenkins, K.6
-
8
-
-
0030235194
-
Asynchronous FPGA architectures
-
Sep.
-
R. E. Payne, “Asynchronous FPGA architectures,” Proc. IEE—Comp. Digit. Tech., vol. 143, no. 5, Sep. 1996.
-
(1996)
Proc. IEE—Comp. Digit. Tech.
, vol.143
, Issue.5
-
-
Payne, R.E.1
-
11
-
-
0024683698
-
Micropipelines
-
Jun.
-
I. E. Sutherland, “Micropipelines,” Comm. ACM, vol. 32, no. 6, pp. 720–738, Jun. 1989.
-
(1989)
Comm. ACM
, vol.32
, Issue.6
, pp. 720-738
-
-
Sutherland, I.E.1
-
12
-
-
0003795268
-
Self-timed rings and their application to division
-
Comp. Sci. Dep., Univ. of Utah, Salt Lake City Jun.
-
T. E. Williams, “Self-timed rings and their application to division,” Ph.D. dissertation, Comp. Sci. Dep., Univ. of Utah, Salt Lake City, Jun. 1991.
-
(1991)
Ph.D. dissertation
-
-
Williams, T.E.1
-
13
-
-
0035439649
-
A new control circuit for asynchronous micropipelines
-
Oct.
-
C. Choy, J. Butas, J. Povazanec, and C. Chan, “A new control circuit for asynchronous micropipelines,” IEEE Trans. Comp., vol. 50, no. 10, pp. 992–997, Oct. 2001.
-
(2001)
IEEE Trans. Comp.
, vol.50
, Issue.10
, pp. 992-997
-
-
Choy, C.1
Butas, J.2
Povazanec, J.3
Chan, C.4
-
16
-
-
0030173207
-
Four-phase micropipeline latch control circuits
-
Jun.
-
S. B. Furber and P. Day, “Four-phase micropipeline latch control circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 4, no. 2, pp. 247–253, Jun. 1996.
-
(1996)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.4
, Issue.2
, pp. 247-253
-
-
Furber, S.B.1
Day, P.2
-
17
-
-
0003795268
-
Self-timed rings and their application to division
-
Comp. Syst. Lab., Stanford Univ., Stanford, CA
-
T. E. Williams, “Self-timed rings and their application to division,” Ph.D. dissertation, Comp. Syst. Lab., Stanford Univ., Stanford, CA, 1991.
-
(1991)
Ph.D. dissertation
-
-
Williams, T.E.1
-
18
-
-
26844507249
-
Self-Controlling asynchronous processor (SCAP)—A system on programmable chip (SOPC)
-
Faculty of Electron. Eng., G.I.K. Institute, Topi, Pakistan Feb.
-
Y. Zafar, “Self-Controlling asynchronous processor (SCAP)—A system on programmable chip (SOPC),” M.S. thesis, Faculty of Electron. Eng., G.I.K. Institute, Topi, Pakistan, Feb. 2003.
-
(2003)
M.S. thesis
-
-
Zafar, Y.1
-
19
-
-
0042134776
-
Automating the design of an asynchronous DLX microprocessor
-
Anaheim, CA, Jun. 02–06
-
M. Amde, I. Blunno, and C. P. Sotiriou, “Automating the design of an asynchronous DLX microprocessor,” in Proc. 40th Design Autom. Conf. (DAC'03), Anaheim, CA, Jun. 02–06, 2003.
-
(2003)
Proc. 40th Design Autom. Conf. (DAC'03)
-
-
Amde, M.1
Blunno, I.2
Sotiriou, C.P.3
-
20
-
-
85008032713
-
-
[Online]. Available:
-
Power Estimator Sheet SPARTAN IIe [Online]. Available: www.xilinx.com
-
-
-
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