A new control circuit for asynchronous micropipelines

IEEE Transactions on Computers

Volumn 50, Issue 9, 2001, Pages 992-997

  Choy, Chiu Sing ^a   Butas, Jan ^a   Povazanec, Juraj ^b   Chan, Cheong Fat ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Asynchronous design; Dual rail coding; Micropipeline; Zero overhead

Indexed keywords

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; NETWORK PROTOCOLS; SIGNAL ENCODING;

ASYNCHRONOUS DESIGN; DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC; DUAL RAIL CODING; EDGE TRIGGERED LATCHES; LOCALLY DISTRIBUTED MICROPIPELINES; ZERO OVERHEAD;

PIPELINE PROCESSING SYSTEMS;

EID: 0035439649     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.954514     Document Type: Article

References (16)

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