Development of a large-scale TEG for evaluation and analysis of yield and variation

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 2, 2004, Pages 111-122

  Yamamoto, Masaharu ^a   Endo, Hitoshi ^b   Masuda, Hiroo ^a  

^a Semiconduct Technol Acad Res C   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Address decoder; Charge up; Correlation analysis; Damage; Electrical dimension; Large scale; Pattern density; Periodicity; TEG; Test structure; Variation; Wafer map; Yield

Indexed keywords

LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; ROM; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

ADDRESS DECODERS; CHARGE UP; CORRELATION ANALYSIS; ELECTRICAL DIMENSION; HISTOGRAMS; TEST STRUCTURE; VARIATION; WAFER MAP; YIELD;

CMOS INTEGRATED CIRCUITS;

EID: 2642521989     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.826937     Document Type: Conference Paper

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