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Volumn , Issue , 2002, Pages 55-59

An assessment of Physical and Electrical Design Rule based Statistical Process Monitoring and Modeling (PEDR-SPMM): For foundry manufacturing line of multiple-product mixed-run

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC VARIABLES MEASUREMENT; PRINCIPAL COMPONENT ANALYSIS; PROCESS CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; STATISTICAL METHODS; TECHNOLOGY;

EID: 0038495581     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (8)
  • 1
    • 0027595303 scopus 로고
    • Predictive worst case statistical modeling of 0.8 um BICOMS bipolar transistors: A methodology based on process and mixed device/circuit level simulators
    • May
    • I. C. Kizilyalli, T. E. Ham, K. Singhal, J. W. Kearney, W. Lin and M. J. Thoma, "Predictive worst case statistical modeling of 0.8 um BICOMS bipolar transistors: a methodology based on process and mixed device/circuit level simulators", IEEE Trans. Electron Device, Vol. 40, No. 5, pp. 966-972, May, 1993.
    • (1993) IEEE Trans. Electron Device , vol.40 , Issue.5 , pp. 966-972
    • Kizilyalli, I.C.1    Ham, T.E.2    Singhal, K.3    Kearney, J.W.4    Lin, W.5    Thoma, M.J.6
  • 2
    • 0028480268 scopus 로고
    • Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design
    • Aug.
    • J.A. Power, B. Donnellanm, A. Mathewson and W.A. Lane, "Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design", IEEE Trans. Semiconductor Manufacturing, Vol. 7, No. 3, pp. 306 - 318, Aug., 1994.
    • (1994) IEEE Trans. Semiconductor Manufacturing , vol.7 , Issue.3 , pp. 306-318
    • Power, J.A.1    Donnellanm, B.2    Mathewson, A.3    Lane, W.A.4
  • 3
    • 0030216579 scopus 로고    scopus 로고
    • A statistical methodology as applied to a 256 Mbit DRAM pass transistor design
    • Aug.
    • P. K. Mozumder, and A. Chatterjee, "A statistical methodology as applied to a 256 Mbit DRAM pass transistor design", IEEE Trans. Semiconductor Manufacturing, Vol. 9, No. 3, pp. 437-446, Aug., 1996.
    • (1996) IEEE Trans. Semiconductor Manufacturing , vol.9 , Issue.3 , pp. 437-446
    • Mozumder, P.K.1    Chatterjee, A.2
  • 5
    • 0033350553 scopus 로고    scopus 로고
    • Statistical device models from worst case files and electrical test data
    • Nov.
    • K. Singhal and V. Visvanathan, "Statistical device models from worst case files and electrical test data," IEEE Trans. Semiconductor Manufacturing, Vol. 12, No. 34, pp. 470-484, Nov., 1999.
    • (1999) IEEE Trans. Semiconductor Manufacturing , vol.12 , Issue.34 , pp. 470-484
    • Singhal, K.1    Visvanathan, V.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.