Development of a large-scale TEG for evaluation and analysis of yield and variation

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 53-58

  Yamamoto, Masaharu ^a   Endo, Hitoshi ^a,b   Masuda, Hiroo ^a  

^a Semiconduct Technol Acad Res C   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; DATABASE SYSTEMS; LARGE SCALE SYSTEMS; SCANNING ELECTRON MICROSCOPY; STATISTICAL METHODS; STRESS ANALYSIS;

STRATEGIC TECHNOLOGY;

MICROELECTRONICS;

EID: 0037966386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. Y. Shimizu et al. ICMTS, Proc., p.49, (2002)
3. C. Hess et al., ICMTS, Proc., p.189, (2002)
4. K. Mlyamoto et al., IEDM, p.36.4.1, (2000)
5. M.W. Cresswell et al. ICMTS, Proc., p. 183, (2001)
6. S. Smith et al., ICMTS, Proc., p.195, (2001)
7. K. Y. Doong et al., ICMTS, Proc., p.55, (2002)
8. R. v. Langevelde et al., "Gate current: Modeling", IEDM, (2001)