Evaluation of the issues involved with test structures for the measurement of sheet resistance and linewidth of copper damascene interconnect

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2001, Pages 195-200

  Smith, S ^a   Walton, A J ^a   Ross, A W S ^a   Bodammer, G K H ^a   Stevenson, J T M ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; DIFFUSION; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE STRUCTURES;

COPPER DAMASCENE INTERCONNECT; DIFFUSION BARRIER LAYERS; DISHING; LINEWIDTH MEASUREMENT; SHEET RESISTANCE MEASUREMENT; TEST STRUCTURES;

INTEGRATED CIRCUITS;

EID: 0034867508     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Tantalum, copper and damascene: The future of interconnects
2. Requirements for dual-damascene cu-linewidth resistivity measurements
3. On the impact of dishing in metal CMP processes on circuit performance
4. Modeling CMP for copper dual damascene interconnects
5. Analysis of the Greek cross, a Van der Pauw structure with finite contacts
6. Design considerations for the cross-bridge sheet resistor
7. Future interconnect technologies and copper metallization