Resistor matching characterization for process development using D/A converter

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2001, Pages 219-222

  Katakam, S ^a   Tranchina, B ^a   Bordelon, J ^a   Ramaswamy, A ^a   Choi, W ^a   Chu, S ^a  

^a TestChip Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; INTEGRATED CIRCUIT LAYOUT; RESISTORS; SCHEMATIC DIAGRAMS;

RESISTOR MISMATCH CHARACTERIZATION; WAFER LEVEL TEST;

INTEGRATED CIRCUIT TESTING;

EID: 0034859928     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Characterization and modeling of mismatch in MOS transistors for precise analog design
2. Matching properties of MOS transistors
3. Design of matching test structures