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Volumn , Issue , 2005, Pages 187-194

Integration challenges for multi-gate devices

Author keywords

[No Author keywords available]

Indexed keywords


EID: 25844498896     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502627     Document Type: Conference Paper
Times cited : (14)

References (21)
  • 4
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    • FinFet - A self-aligned double-gate MOSFET scalable to 20 nm
    • December
    • D. Hisamoto et al.,"FinFet - A Self-Aligned Double-Gate MOSFET Scalable to 20 nm", IEEE Trans. Electron Dev., vol. 47, no. 12, December 2000, pp. 2320-2325
    • (2000) IEEE Trans. Electron Dev. , vol.47 , Issue.12 , pp. 2320-2325
    • Hisamoto, D.1
  • 6
    • 0036932378 scopus 로고    scopus 로고
    • 25 nm CMOS Omega FETs
    • F.-L. Yang et al., "25 nm CMOS Omega FETs", IEDM Techn. Dig., 2002, p. 255-258
    • (2002) IEDM Techn. Dig. , pp. 255-258
    • Yang, F.-L.1
  • 8
    • 21644472774 scopus 로고    scopus 로고
    • 2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
    • 2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography", IEDM Techn. Dig., 2004, p. 269-272
    • (2004) IEDM Techn. Dig. , pp. 269-272
    • Nackaerts, A.1
  • 9
    • 0036163060 scopus 로고    scopus 로고
    • Nanoscale CMOS spacer FinFET for the terabit era
    • Y.-K. Choi, T.-J. King and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era", IEEE Electron Device Lett., vol. 23, no. 1, 2002, pp. 25-27
    • (2002) IEEE Electron Device Lett. , vol.23 , Issue.1 , pp. 25-27
    • Choi, Y.-K.1    King, T.-J.2    Hu, C.3
  • 15
    • 0036923594 scopus 로고    scopus 로고
    • Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
    • J. Kedzierski et al., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation", IEDM Techn. Dig., 2002, pp. 247-250.
    • (2002) IEDM Techn. Dig. , pp. 247-250
    • Kedzierski, J.1
  • 16
    • 0842266648 scopus 로고    scopus 로고
    • Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)
    • J. Kedzierski et al., "Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)", IEDM Techn. Dig., 2003, pp. 315-318.
    • (2003) IEDM Techn. Dig. , pp. 315-318
    • Kedzierski, J.1
  • 17
    • 25844493324 scopus 로고    scopus 로고
    • CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
    • to be presented at the
    • K.G. Anil et al., "CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach", to be presented at the VLSI Symposium 2005
    • VLSI Symposium 2005
    • Anil, K.G.1
  • 19
    • 3943110263 scopus 로고    scopus 로고
    • A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm Fin widths applicable for the 45-nm CMOS node
    • N. Collaert et al.,"A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devices With 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node", IEEE Electron Device Lett., vol. 25, no. 8, 2004, p. 568-570
    • (2004) IEEE Electron Device Lett. , vol.25 , Issue.8 , pp. 568-570
    • Collaert, N.1
  • 20
    • 0037480885 scopus 로고    scopus 로고
    • Extension and source/drain design for high performance FinFET devices
    • J. Kedzierski et al., "Extension and Source/Drain Design for High Performance FinFET Devices", IEEE Trans. on Electron Dev., vol. 50, no. 4, 2003, pp. 952-958
    • (2003) IEEE Trans. on Electron Dev. , vol.50 , Issue.4 , pp. 952-958
    • Kedzierski, J.1
  • 21
    • 25844490171 scopus 로고    scopus 로고
    • Analysis of the parasitic source/drain resistance in multiple gate field effect transistors
    • accepted for publication
    • A. Dixit et al., "Analysis of the Parasitic Source/Drain Resistance in Multiple Gate Field Effect Transistors", accepted for publication in IEEE Trans. on Electron Dev.
    • IEEE Trans. on Electron Dev.
    • Dixit, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.