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1
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16244389948
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Experimental gate misalignment analysis on double gate SOI MOSFETs
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J. Widiez, F. Dauge, M. Vinet, T. Poiroux, B. Previtali, M. Mouis and S. Deleonibus, "Experimental gate misalignment analysis on double gate SOI MOSFETs", Proceedings of the IEEE SOI Conference, 2004, p. 185-186
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(2004)
Proceedings of the IEEE SOI Conference
, pp. 185-186
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Widiez, J.1
Dauge, F.2
Vinet, M.3
Poiroux, T.4
Previtali, B.5
Mouis, M.6
Deleonibus, S.7
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2
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17644439016
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Highly performant double gate MOSFET realized with SON process
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S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R; Pantel, S. Descombes, D. Dutartre, Y. Morand, M.P. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteanu, J.-L. Autran and T. Skotnicki, "Highly performant double gate MOSFET realized with SON process", IEDM Techn. Dig., 2003, p. 449-452
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(2003)
IEDM Techn. Dig.
, pp. 449-452
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Harrison, S.1
Coronel, P.2
Leverd, F.3
Cerutti, R.4
Palla, R.5
Delille, D.6
Borel, S.7
Jullian, S.8
Pantel, R.9
Descombes, S.10
Dutartre, D.11
Morand, Y.12
Samson, M.P.13
Lenoble, D.14
Talbot, A.15
Villaret, A.16
Monfray, S.17
Mazoyer, P.18
Bustos, J.19
Brut, H.20
Cros, A.21
Munteanu, D.22
Autran, J.-L.23
Skotnicki, T.24
more..
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3
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0035424985
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Short-channel vertical sidewall MOSFETs
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August
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T. Schulz, W. Rosner, L. Risch, A. Korbel and U. Langmann, "Short-channel vertical sidewall MOSFETs", IEEE Trans. Electron Dev., vol. 48, no. 8, August 2001, pp. 1783-1788
-
(2001)
IEEE Trans. Electron Dev.
, vol.48
, Issue.8
, pp. 1783-1788
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Schulz, T.1
Rosner, W.2
Risch, L.3
Korbel, A.4
Langmann, U.5
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4
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29044440093
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FinFet - A self-aligned double-gate MOSFET scalable to 20 nm
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December
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D. Hisamoto et al.,"FinFet - A Self-Aligned Double-Gate MOSFET Scalable to 20 nm", IEEE Trans. Electron Dev., vol. 47, no. 12, December 2000, pp. 2320-2325
-
(2000)
IEEE Trans. Electron Dev.
, vol.47
, Issue.12
, pp. 2320-2325
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Hisamoto, D.1
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5
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0035423513
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Pi-gate SOI MOSFET
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J.-T. Park, J.-P. Colinge and C. H. Diaz, "Pi-Gate SOI MOSFET", IEEE Electron Device Lett., vol. 22, no. 8, 2001, pp. 405-406
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.8
, pp. 405-406
-
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Park, J.-T.1
Colinge, J.-P.2
Diaz, C.H.3
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6
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0036932378
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25 nm CMOS Omega FETs
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F.-L. Yang et al., "25 nm CMOS Omega FETs", IEDM Techn. Dig., 2002, p. 255-258
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(2002)
IEDM Techn. Dig.
, pp. 255-258
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Yang, F.-L.1
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7
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0038104277
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High performance fully-depleted tri-gate CMOS transistors
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B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios and R. Chau, "High performance fully-depleted tri-gate CMOS transistors", IEEE Electron Device Lett., vol. 24, no. 4, 2003, pp. 263-265
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.4
, pp. 263-265
-
-
Doyle, B.S.1
Datta, S.2
Doczy, M.3
Hareland, S.4
Jin, B.5
Kavalieros, J.6
Linton, T.7
Murthy, A.8
Rios, R.9
Chau, R.10
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8
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21644472774
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2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
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2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography", IEDM Techn. Dig., 2004, p. 269-272
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(2004)
IEDM Techn. Dig.
, pp. 269-272
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Nackaerts, A.1
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9
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0036163060
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Nanoscale CMOS spacer FinFET for the terabit era
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Y.-K. Choi, T.-J. King and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era", IEEE Electron Device Lett., vol. 23, no. 1, 2002, pp. 25-27
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(2002)
IEEE Electron Device Lett.
, vol.23
, Issue.1
, pp. 25-27
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Choi, Y.-K.1
King, T.-J.2
Hu, C.3
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10
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84907703268
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Layout density analysis of FinFETs
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K.G. Anil, K. Henson, S. Biesemans, and N. Collaert, "Layout density analysis of FinFETs", European Solid-State Device Research, 2003, p. 139-142
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(2003)
European Solid-State Device Research
, pp. 139-142
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Anil, K.G.1
Henson, K.2
Biesemans, S.3
Collaert, N.4
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11
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84881738377
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Challenges in patterning 45nm node multiple-gate devices and SRAM cells
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M. Ercken, C. Delvaux, C. Baerts, S. Locorotondo, B. Degroote, V. Wiaux, A. Nackaerts, R. Rooyackers, S. Verhaegen and I. Pollentier, "Challenges in patterning 45nm node multiple-gate devices and SRAM cells", Proceedings 41st Interface Symposium,
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Proceedings 41st Interface Symposium
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Ercken, M.1
Delvaux, C.2
Baerts, C.3
Locorotondo, S.4
Degroote, B.5
Wiaux, V.6
Nackaerts, A.7
Rooyackers, R.8
Verhaegen, S.9
Pollentier, I.10
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12
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25844458632
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The etchback approach: Enlarged process window for MuGFET gate etching
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to be presented at the
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B. Degroote, N. Collaert, R. Rooyackers, M.R. Baklanov, W. Boullart, E. Kunnen, M. Jurczak, S. Vanhaelemeersch, "The etchback approach: enlarged process window for MuGFET gate etching", to be presented at the AVS ICMI 2005 conference
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AVS ICMI 2005 Conference
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Degroote, B.1
Collaert, N.2
Rooyackers, R.3
Baklanov, M.R.4
Boullart, W.5
Kunnen, E.6
Jurczak, M.7
Vanhaelemeersch, S.8
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13
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27144512245
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NMOS and PMOS triple gate devices with midgap metal gate on oxynitride and Hf based gate dielectrics
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to be presented at the
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K. Henson, N. Collaert, M. Demand, M. Goodwin, S. Brus, R. Rooyackers, A. van Ammel, B. Degroote, M. Ercken, C. Baerts, K. G. Anil, A. Dixit, S. Beckx, T. Schram, W. Deweerd, W. Boullart, M. Schaekers, S. De Gendt, K. De Meyer, Y. Yim, J.C. Hooker, M. Jurczak, S. Biesemans, "NMOS and PMOS Triple Gate Devices with Midgap Metal Gate on Oxynitride and Hf Based Gate Dielectrics", to be presented at the VLSI-TSA-TECH conference 2005
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VLSI-TSA-TECH Conference 2005
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Henson, K.1
Collaert, N.2
Demand, M.3
Goodwin, M.4
Brus, S.5
Rooyackers, R.6
Van Ammel, A.7
Degroote, B.8
Ercken, M.9
Baerts, C.10
Anil, K.G.11
Dixit, A.12
Beckx, S.13
Schram, T.14
Deweerd, W.15
Boullart, W.16
Schaekers, M.17
De Gendt, S.18
De Meyer, K.19
Yim, Y.20
Hooker, J.C.21
Jurczak, M.22
Biesemans, S.23
more..
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14
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0035717522
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Totally suicided (CoSi2) Polysilicon: A novel approach to very low-resistive gate without metal CMP nor etching
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B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, "Totally suicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate without metal CMP nor etching", IEDM Techn. Dig., 2001, pp. 825-828.
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(2001)
IEDM Techn. Dig.
, pp. 825-828
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Tavel, B.1
Skotnicki, T.2
Pares, G.3
Carriere, N.4
Rivoire, M.5
Leverd, F.6
Julien, C.7
Torres, J.8
Pantel, R.9
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15
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0036923594
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Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
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J. Kedzierski et al., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation", IEDM Techn. Dig., 2002, pp. 247-250.
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(2002)
IEDM Techn. Dig.
, pp. 247-250
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Kedzierski, J.1
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16
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0842266648
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Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)
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J. Kedzierski et al., "Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)", IEDM Techn. Dig., 2003, pp. 315-318.
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(2003)
IEDM Techn. Dig.
, pp. 315-318
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Kedzierski, J.1
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17
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25844493324
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CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
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to be presented at the
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K.G. Anil et al., "CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach", to be presented at the VLSI Symposium 2005
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VLSI Symposium 2005
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Anil, K.G.1
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18
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33745134066
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25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
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to be presented at the
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P. Verheyen, N. Collaert, R. Loo, R. Rooyackers, D. Shamiryan, A. De Keersgieter, G. Eneman, F. Leys, A. Dixit, M. Goodwin, Y. Yim, M. Caymax, K. De Meyer, M. Jurczak, P. Absil and S. Biesemans, "25% Drive Current improvement for p-type Multiple Gate FET (MuGFET) Devices by the Introduction of Recessed Si0.8Ge0.2 in the Source and Drain Regions", to be presented at the VLSI Symposium 2005
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VLSI Symposium 2005
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Verheyen, P.1
Collaert, N.2
Loo, R.3
Rooyackers, R.4
Shamiryan, D.5
De Keersgieter, A.6
Eneman, G.7
Leys, F.8
Dixit, A.9
Goodwin, M.10
Yim, Y.11
Caymax, M.12
De Meyer, K.13
Jurczak, M.14
Absil, P.15
Biesemans, S.16
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19
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3943110263
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A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm Fin widths applicable for the 45-nm CMOS node
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N. Collaert et al.,"A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devices With 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node", IEEE Electron Device Lett., vol. 25, no. 8, 2004, p. 568-570
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.8
, pp. 568-570
-
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Collaert, N.1
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20
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0037480885
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Extension and source/drain design for high performance FinFET devices
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J. Kedzierski et al., "Extension and Source/Drain Design for High Performance FinFET Devices", IEEE Trans. on Electron Dev., vol. 50, no. 4, 2003, pp. 952-958
-
(2003)
IEEE Trans. on Electron Dev.
, vol.50
, Issue.4
, pp. 952-958
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Kedzierski, J.1
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21
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25844490171
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Analysis of the parasitic source/drain resistance in multiple gate field effect transistors
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accepted for publication
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A. Dixit et al., "Analysis of the Parasitic Source/Drain Resistance in Multiple Gate Field Effect Transistors", accepted for publication in IEEE Trans. on Electron Dev.
-
IEEE Trans. on Electron Dev.
-
-
Dixit, A.1
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