A scalable and programmable simplicial CNN digital pixel processor architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 5, 2004, Pages 988-996

  Mandolesi, Pablo S ^a,b   Julian, Pedro ^a,b,c   Andreou, Andreas G ^a  

^a Johns Hopkins University   (United States)

^b UNIVERSIDAD NACIONAL DEL SUR   (Argentina)

^c Facultad de Ciencias Naturales e Instituto M Lillo   (Argentina)

Author keywords

Cellular neural networks (CNNs); CMOS imager sensor; Digital pixel; Image processing; Pixel level processing; Vision chips

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; IMAGE PROCESSING; IMAGE QUALITY; IMAGE SENSORS; MATHEMATICAL MODELS;

DATA IMAGE PROCESSOR; DIGITAL CIRCUITS AND WIRINGS; DIGITAL PIXEL; DIGITAL PIXEL PROCESSOR ARCHITECTURE; PIXEL LEVEL PROCESSING; VISION CHIPS;

CELLULAR NEURAL NETWORKS;

EID: 2542644075     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.827626     Document Type: Article

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