A 590,000 transistor 48,000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina

Proceedings - 16th Conference on Advanced Research in VLSI, ARVLSI 1995

Volumn , Issue , 1995, Pages 225-240

  Andreou, A G ^a   Boahen, K A ^b  

^a JOHNS HOPKINS UNIVERSITY   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOW POWER ELECTRONICS; PIXELS; SILICON; VLSI CIRCUITS;

AREA EFFICIENCY; CMOS TECHNOLOGY; EDGE ENHANCEMENTS; EDGE ENHANCING; PHOTOTRANSDUCTION; SILICON RETINA; SUBTHRESHOLD CMOS; ULTRA LOW POWER DISSIPATIONS;

IMAGE ENHANCEMENT;

EID: 0042251695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1995.515623     Document Type: Conference Paper

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