A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 7, 1997, Pages 1013-1025

  Domínguez Castro, Rafael ^a,b,e,f   Espejo, Servando ^a,b,e,f,g   Rodríguez Vázquez, Angel ^a,b,f,h   Carmona, Ricardo A ^b,c,i,j   Földesy, Péter ^d   Zarándy, Ákos ^d   Szolgay, Péter ^d   Szirányi, Tamás ^d   Roska, Tamás ^a,d  

^a IEEE   (Spain)

^b UNIVERSITY OF SEVILLE   (Spain)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d INSTITUTE OF EXPERIMENTAL MEDICINE   (Hungary)

^e Licenciado en Fis Electronica ^*  (Spain)

^f Department of Analog Circuit Design   (Spain)

^g LUCENT TECHNOLOGIES   (United States)

^h Technical Program Committees

ⁱ INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^j UNIVERSITY OF CALIFORNIA   (United States)

more..

Author keywords

Analog array processors; Cellular neural networks; Focal plane processors; Vision chips

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; FEEDBACK; IMAGE PROCESSING; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; MIXER CIRCUITS; NEURAL NETWORKS; NONLINEAR NETWORKS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING;

BINARY IMAGES; FOCAL PLANE PROCESSORS; ONCHIP NONLINEAR DIGITAL TO ANALOG CONVERTERS (DAC);

PARALLEL PROCESSING SYSTEMS;

EID: 0031188728     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.597292     Document Type: Article

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