A piecewise-linear simplicial coupling cell for CNN gray-level image processing

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 7, 2002, Pages 904-913

  Julian, Pedro ^a,b,c,d   Dogaru, Radu ^a,e   Chua, Leon O ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c CONICET ^*  (Argentina)

^d UNIVERSIDAD NACIONAL DEL SUR   (Argentina)

^e UNIVERSITY POLITEHNICA OF BUCHAREST   (Romania)

Author keywords

Cell neural networks; Image processing; Piecewise linear approximation

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; CELLS; COMPUTATIONAL COMPLEXITY; DIFFERENTIAL EQUATIONS; EDGE DETECTION; IMAGE PROCESSING; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES;

CELL FUNCTION; COUPLING CELL; COUPLING FUNCTION; GRAY LEVEL; HILBERT SPACE; IMPULSIVE NOISE REMOVAL;

CELLULAR NEURAL NETWORKS;

EID: 0036647565     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.800464     Document Type: Article

References (18)

1. Cellular neural networks: Theory
2. CNN: A vision of complexity
3. Pyramidal cells: A novel class of adaptive coupling cells and their applications for cellular neural networks
4. Efficient implementation of neighborhood logic for cellular automata via the cellular neural network universal machine
5. Universal CNN cells
6. Physical modeling of RTD based CNN cells
7. A method of multi-dimensional linear interpolation
8. Solving nonlinear resistive networks using piecewise-linear analysis and simplicial subdivision
9. A high level canonical piecewise-linear representation: Theory and applications
10. High level canonical piecewise linear representation using a simplicial partition
11. Orthonormal high level canonical PWL functions with applications to model reduction
12. A robust and efficient CNN cell circuit using simplicial neuro-fuzzy inferences for fast image processing
13. A sparse method for the canonical representation and approximation of PWL functions
14. The simplicial neural cell and its mixed-signal circuit implementation: An efficient neural network architecture for intelligent signal processing in portable multimedia applications
15. A 150 MHz graphics rendering processor with 256 Mb embedded DRAM
16. A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline arcjotecture
17. VLSI implementation of a modular and programmable neural architecture