A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 320-321

  Tang, Stephen ^a   Hsu, Steven ^a   Ye, Yibin ^a   Tschanz, James ^a   Somasekhar, Dinesh ^a   Narendra, Siva ^a   Lu, Shih Lien ^a   Krishnamurthy, Ram ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOS DEVICES; PERFORMANCE; VLSI CIRCUITS;

LEAKAGE BYPASS WITH STACK FORCING; LEAKAGE-TOLERANT DYNAMIC REGISTER FILE; SOURCE FOLLOWER NMOS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242526896     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Anders et al., 2001 Symp. VLSI Circuits, pp. 23-24.
2. A. Alvandpour et al., 2001 Symp. VLSI Circuits, pp. 29-30.
3. R. Krishnamurthy et al., 2001 Symp. VLSI Circuits, pp 25-26.
4. S. Vangel et al., 2002 ISSCC, paper 25.2.
5. Y. Ye et. al., 1998 Symp. VLSI Circuits, pp. 40-41.