Integrated circuit DFM framework for deep sub-wavelength processes

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5756, Issue , 2005, Pages 39-50

  Torres, J A ^a   Berglund, C N ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

DFM; Litho compliant; Microlithography; OPC; Process models; RET compliant; Timing analysis

Indexed keywords

DESIGN FOR MANUFACTURING (DFM); LITHO-COMPLIANT; OPC; PROCESS MODELS; RET-COMPLIANT; TIMING ANALYSIS;

INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; MATHEMATICAL MODELS; PROBLEM SOLVING; ROBUSTNESS (CONTROL SYSTEMS);

INTEGRATED CIRCUIT MANUFACTURE;

EID: 25144453794     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.599044     Document Type: Conference Paper

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