A quantitative approach to nonlinear process design rule scaling [VLSI]

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 99-112

  Gold, Spencer M ^a   Bernhardt, Bruce ^b   Brown, Richard B ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST ESTIMATING; COSTS; GALLIUM ARSENIDE; GALLIUM COMPOUNDS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; METAL ANALYSIS; NONLINEAR ANALYSIS; PROCESS DESIGN; VLSI CIRCUITS;

CAPITAL EQUIPMENT ACQUISITIONS; COST/BENEFIT RATIO; DELAY IMPROVEMENTS; NON-LINEAR DESIGN; NON-LINEAR SCALING; QUANTITATIVE APPROACH; QUANTITATIVE METHODOLOGY; QUANTITATIVE METRIC;

COST BENEFIT ANALYSIS;

EID: 84889897012     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756041     Document Type: Conference Paper

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