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Volumn , Issue , 2004, Pages 202-210

Fast and low-cost clock deskew buffer

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK BUFFERS; CLOCK CYCLES; POWER SUPPLY; SYSTEM OPERATION;

EID: 24944443526     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347841     Document Type: Conference Paper
Times cited : (13)

References (23)
  • 1
    • 33947698137 scopus 로고    scopus 로고
    • New defect behavior at 130nm and beyon emerging ideas contribution
    • Extended Abstract
    • R. Aitken. New Defect Behavior at 130nm and Beyon Emerging Ideas Contribution, Extended Abstract. In IEEE European Test Symp. - Informal Digest Papers, pages 279 - 284, 2004.
    • (2004) IEEE European Test Symp. - Informal Digest Papers , pp. 279-284
    • Aitken, R.1
  • 2
    • 0000239119 scopus 로고    scopus 로고
    • The challenge of signal integrity in deep-submicrometer CMOS technology
    • F. Caignet, D. Delmas-Bendhia, and E. Sicard. The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology. In Proc. of IEEE, pages 556 - 573, 2001.
    • (2001) Proc. of IEEE , pp. 556-573
    • Caignet, F.1    Delmas-Bendhia, D.2    Sicard, E.3
  • 3
    • 0030651637 scopus 로고    scopus 로고
    • Analysis of ground bounce in deep sub-mmicron circuits
    • Y. Chang, K. Gupta, and C. Koh. Analysis of Ground Bounce in Deep Sub-Mmicron Circuits. In Proc. of IEEE VLSI Test Symp., pages 110-116, 1997.
    • (1997) Proc. of IEEE VLSI Test Symp. , pp. 110-116
    • Chang, Y.1    Gupta, K.2    Koh, C.3
  • 13
    • 0032180220 scopus 로고    scopus 로고
    • Concurrent checking of clock signals' correctness
    • C. Metra, M. Favalli, and B. Riccò. Concurrent Checking of Clock Signals' Correctness. IEEE Design k Test, pages 42-48, 1998.
    • (1998) IEEE Design k Test , pp. 42-48
    • Metra, C.1    Favalli, M.2    Riccò, B.3
  • 14
    • 3042571556 scopus 로고    scopus 로고
    • Implications of clock distribution faults and issues with screening them during manufacturing testing
    • May
    • C. Metra, S. D. Francescantonio, and T. Mak. Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Comput., 53(5):531 - 546, May 2004.
    • (2004) IEEE Trans. Comput. , vol.53 , Issue.5 , pp. 531-546
    • Metra, C.1    Francescantonio, S.D.2    Mak, T.3
  • 15
    • 0036443083 scopus 로고    scopus 로고
    • Clock faults' impact on manufacturing testing and their possible detection through on-line testing
    • October
    • C. Metra, S. D. Francescantonio, and T. M. Mak. Clock Faults' Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. Proc. of IEEE Int. Test Conf., pages 100-109, October 2002.
    • (2002) Proc. of IEEE Int. Test Conf. , pp. 100-109
    • Metra, C.1    Francescantonio, S.D.2    Mak, T.M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.