MicroGP-An evolutionary assembly program generator

Genetic Programming and Evolvable Machines

Volumn 6, Issue 3, 2005, Pages 247-263

  Squillero, Giovanni ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Assembly programs generation; Evolutionary algorithms; Micro processors

Indexed keywords

COMPUTER SIMULATION; EVOLUTIONARY ALGORITHMS; FEEDBACK; FUNCTIONS; LIBRARIES; MICROPROCESSOR CHIPS; QUERY LANGUAGES;

ASSEMBLY PROGRAMS GENERATION; DESIGN VALIDATION; FUNCTIONAL TESTS; MICRO-PROCESSORS;

PROGRAM ASSEMBLERS;

EID: 24644454372     PISSN: 13892576     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10710-005-2985-x     Document Type: Article

References (32)

1. R. M. Friedberg, "A learning machine: Part I," IBM Journal of Research and Development, vol. 2, no. 1, pp. 2-13, 1958.
2. R. M. Friedberg, B. Dunham, and J. H. North, "A learning machine: Part II," IBM Journal Research and Development, vol. 3, pp. 183-191, 1959.
3. J. R. Koza, "Genetic programming," in Encyclopedia of Computer Science and Technology, A. Kent and J. Williams (Eds.), Marcel Dekker Publisher: New York, NY, USA, vol. 39, 1998, pp. 29-43, ISBN 0-8247-2292-2.
4. J. R. Koza, Genetic Programming: On the Programming of Computers by Means of Natural Selection, MIT-Press: Cambridge, MA, USA, 1992, ISBN 0-262-11170-5.
5. J. R. Koza, Genetic Programming U: Automatic Discovery of Reusable Programs, MIT-Press: Cambridge, MA, USA, 1994, ISBN 0-262-11189-6.
6. A. Fukunaga, A. Stechert, and D. Mutz, "A genome compiler for high performance genetic programming," in Genetic Programming 1998: Proceedings of the 3rd Annual Conference, J. R. Koza, W. Banzhaf, K. Chellapilla, K. Deb, M. Dorigo, D. B. Fogel, M. H. Garzon, D. E. Goldberg, H. Iba, and R. L. Riolo (Eds.), Morgan Kaufmann Publishers: San Francisco, CA, USA, 1998, pp. 86-94.
7. S. Handley, "On the use of a directed acyclic graph to represent a population of computer programs," in Proceedings of the 1994 IEEE World Congress on Computational Intelligence, IEEE: New York, NY, USA, 1994, pp 154-159.
8. R. Poli, "Evolution of graph-like programs with parallel distributed genetic programming," Genetic Algorithms: Proceedings of the 7th International Conference, Thomas Back (Ed.), Morgan Kaufmann: San Francisco, CA, USA, 1997, pp. 346-353.
9. P. Nordin, "A compiling genetic programming system that directly manipulates the machine code," in Advances in Genetic Programming, K. Kinnear (Ed.), MIT-Press: Cambridge, MA, USA, 1994, pp. 311-331.
10. P. Nordin and W. Banzhaf, "Evolving turing-complete programs for a register machine with self-modifying code," in Genetic Algorithms: Proceedings of the 6th International Conference, L. Eshelman (Ed.), Morgan Kaufmann: San Francisco, CA, USA, 1995, pp. 318-327.
11. P. Nordin, W. Banzhaf, and F. Frantone, "Efficient evolution of machine code for CISC architectures using blocks and homologous crossover," in Advances in Genetic Programming III, L. Spector (Ed.), MIT-Press: Cambridge, MA, USA, 1999, pp. 275-299.
12. E. Lukschandl, H. Borgvall, L. Nohle, M. Nordahl, and P. Nordin, "Evolving routing algorithms with the JBGP-system," in Evolutionary Image Analysis, Signal Processing and Telecommunications: First European Workshop, EvoIASP'99 and EuroEcTel'99, R. Poli, H.-M. Voigt, S. Cagnoni, D. Come, G. D. Smith, and T. C. Fogarty (Eds.), Springer-Verlag: Berlin, DE, 1999, pp. 193-202.
13. F. Corno, M. Sonza Reorda, G. Squillero, and M. Violante, "On the test of microprocessor IP Cores," in IEEE Design, Automation & Test in Europe Conference, W. Nebel and A. Jerraya (Eds.), IEEE Computer Society: Los Alamitos, CA, USA, 2001, pp. 209-213.
14. F. Corno, G. Cumani, M. Sonza Reorda and G. Squillero, "Efficient machine-code test-program induction," in Congress on Evolutionary Computation, D. B. Fogel, M. A. El-Sharkawi, X. Yao, G. Greenwood, H. Iba, P. Marrow, and M. Shackleton (Eds.), IEEE: Piscataway, NJ, USA, 2002, pp. 1486-1491.
15. W. Kantschik and W. Banzhaf, "Linear-Graph GP: A New GP Structure," in Genetic Programming: 5th European Conference, J. A. Foster, E. Lutton, J. Miller, C. Ryan, and A. G. B. Tettamanzi (Eds.), Springer-Verlag: Berlin, DE, 2002, pp. 83-92.
16. F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, "Evolutionary test program induction for microprocessor design verification," in 11th Asian Test Symposium, IEEE Computer Society: Los Alamitos, CA, USA, 2002, pp. 368-373.
17. F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, "Exploiting auto-adaptive μGP for highly effective test programs generation," in 5th International Conference on Evolvable Systems: From Biology to Hardware (ICES2003), A. M. Tyrrell, P. C. Haddow, and J. Torresen (Eds.), Springer-Verlag: Berlin, DE, 2003, pp. 262-273.
18. F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, "Automatic test program generation for pipelined processors," in SAC03: 18th ACM Symposium on Applied Computing, H. Iwashita, S. Kowatari, T. Nakata, and F. Hirose (Eds.), ACM: New York, NY, USA, 2003, pp. 736-740.
19. F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, "Fully Automatic Test Program Generation for Microprocessor Cores," in DATE: IEEE Design, Automation & Test in Europe, N. Wehn and D. Verkest (Eds.), IEEE Computer Society: Los Alamitos, CA, USA, 2003, pp. 1006-1011.
20. A. L. Samuel, "Some studies in machine learning using the game of checkers," IBM Journal of Research and Development, vol. 3, no. 3, pp. 210-229, 1959.
21. Also available as: A. L. Samuel, "Some studies in machine learning using the game of checkers," in Computers and Thought, E. A. Feigenbaum, and J. Feldman (Eds.), MIT Press: Cambridge, MA, USA, 1995, pp. 71-105.
22. G. Cabodi, S. Nocco, and S. Quer, "Improving SAT-based bounded model checking by means of BDDb-based approximate traversals," in IEEE Design, Automation & Test in Europe Conference, N. Wehn and D. Verkest (Eds.), IEEE Computer Society: Los Alamitos, CA, USA, 2003, pp. 898-903.
23. H. H. Kwak, I. H. Moon, J. H. Kukula, and T. R. Shiple, "Combinational equivalence checking through function transformation," in International Conference on Computer Aided Design, IEEE: Piscataway, NJ, USA, 2002, pp. 526-533.
24. J. Harrison, "Formal verification at Intel," in IEEE Symposium on Logic in Computer Science, IEEE Computer Society: Los Alamitos, CA, USA, 2003, pp. 45-54.
25. B. Bentley, "Validating the Intel Pentium 4 microprocessor," in Design Automation Conference, ACM: New York, NY, USA, 2001, pp. 244-248.
26. P. Mishra, H. Tomiyama, N. Dutt, and A. Nicolau, "Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units," in DATE: IEEE Design, Automation & Test in Europe, C. D. Kloos and J. da-Franca (Eds.), IEEE Computer Society: Los Alamitos, CA, USA, 2002, pp. 36-43.
27. N. Utamaphethai, R. D. Blanton, and J. P. Shen, "Superscalar processor validation at the microarchitecture level," in 12th IEEE International Conference on VLSI Design, IEEE Computer Society: Los Alamitos, CA, USA, 1999, pp. 300-305.
28. A. Chandra, V. Iyengar, D. Jameson, R. Jawalker, I. Nair, B. Rosen, M. Mullen, J. Yoor, R. Armoni, D. Geist, and Y. Wolfstal, "AVPGEN - a test generator for architecture verification," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE: New York, NY, USA, vol. 3, no. 2, 1995, pp. 188-200.
29. A. Aharon, A. Ba-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "Verification of the IBM RISC System/6000 by dynamic biased pseudo-random test program generator," IBM Systems Journal, vol. 30, no. 4, pp. 527-538, 1991.
30. D. A. Patterson and J. L. Hennessy, Computer Architecture - A Quantitative Approach, 2nd edition, Morgan Kaufmann: CA, USA, 1996, ISBN 1-55860-329-8.
31. P. M. Sailer, and P. M. Sler, DLX Instruction Set Architecture Handbook, Morgan Kaufmann: CA, USA, 1996, ISBN 1-55860-371-9.
32. D. Van Campenhout, T. N. Mudge, and J. P. Hayes, "High-level test generation for design verification of pipelined microprocessors," in Design Automation Conference, IEEE: Piscataway, NJ, USA, 1999, pp. 185-188.