Estimating circuit fault-tolerance by means of transient-fault injection in VHDL

Proceedings - 6th IEEE International On-Line Testing Workshop

Volumn , Issue , 2000, Pages 67-72

  Vargas, F ^a   Amory, A ^a   Velazco, R ^b  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b TIMA LABORATORY   (France)

Author keywords

Error Detection and Correction (EDAC) Techniques; Fault tolerant Complex Circuits Design; High Level Description (VHDL); Radiation Exposed Environments; Reliability Early Estimation; Single Event Upset (SEU)

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ECONOMIC AND SOCIAL EFFECTS; FAULT TOLERANCE; RADIATION HARDENING; RECONFIGURABLE HARDWARE; RELIABILITY;

COMPLEX CIRCUITS; ERROR DETECTION AND CORRECTION; HIGH LEVEL DESCRIPTION; RADIATION ENVIRONMENTS; RADIATION FACILITIES; RELIABILITY LEVEL; SINGLE EVENT UPSETS; TRANSIENT FAULTS;

REDUNDANCY;

EID: 0142206123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2000.856614     Document Type: Conference Paper

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