Detailed comparison of dependability analyses performed at rt and gate levels

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 336-343

  Ammari, A ^a   Leveugle, R ^a   Sonza Reorda, M ^b   Violante, M ^b  

^a TIMA LABORATORY   (France)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; FAULT TOLERANCE; REGRESSION ANALYSIS;

BEHAVIORAL LEVEL; DEPENDABILITY ANALYSIS; ERROR PROPAGATION PATHS; GATE LEVELS; POTENTIAL EFFECTS;

RECONFIGURABLE HARDWARE;

EID: 84971277833     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250129     Document Type: Conference Paper

References (11)

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11. http://www.8051.free.fr