Design of high performance double edge-triggered flip-flops

IEE Proceedings: Circuits, Devices and Systems

Volumn 147, Issue 5, 2000, Pages 283-290

  Mishra, S M ^a   Rofail, S S ^a   Yeo, K S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE EDGE-TRIGGERED FLIP FLOPS (DETFF);

ENERGY DISSIPATION; LOGIC CIRCUITS; TRANSISTORS;

FLIP FLOP CIRCUITS;

EID: 0034297624     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20000672     Document Type: Article

References (13)

1. KURODA, T. and SAK.URAI, T. 'Low-power circuit design for multimedia CMOS VLSI's'. Proceedings of conference on Synthesis and system integration mixed technology (SASIMI), 1996, pp. 3-10
2. YUAN, J. and SVENSSON, C: 'New single-clock CMOS latches and flip-flops with improved speed and power savinss', IEEE J. SolidState Circuits, 1997, 32, (1), pp. 62-69
3. AFGHAHI, M. and YUAN, J. 'Double cdce triccercd flip-flops for hieh-speed CMOS circuits', IEEE J. Solid-Slate Circuits. 1991, 26, (8), pp. 1168-1170
4. GAGO, A. ESCANO, R. and HIDALGO, J.A. 'Reduced implementation of D-t>pe DET flip-flops', IEEE J. Solid-Stale Ciraiits, 1993, 28, (3), pp. 40
5. BLAIR, CM. 'Comments on new single-clock CMOS latches and flip-flops with improved speed and power savincs', IEEE J. SolidState Ciraiits, 1997, 32, (10), pp. 1610-1611
6. NJOLSTAD, T. and AAS, E.J. Tower consumption and performance of low-voltage bit-serial adders'. Proceedings of IEEE international symposium on Circuits and systems (ISCAS96), 1996, Vol. 4, pp. 45-48
7. MISHRA, S.M. YEO, K.S. and ROFAIL, S.S. 'Altering transistor positions impact on the performance and power dissipation of dynamic latches and flip-flops', IEE Proc. Circuits, Devices Syst.1999, 146, (5), pp. 279-284
8. HOSSAIN, R. WRONSKI, L. and ALB1CKI, A. 'Low power desicn using double edee triggered flip-flops', IEEE Trans. VLSI Syst.1994, 2, (2), pp. 261-265
9. PEDRAM, M. WU, Q. and WU, X. 'A new design of double edge triggered flip-flops'. Proceedings of the Asia and South Pacific conference on Design automation (ASP DAC), 1998, pp. 417-421
10. DOPPERPUHL, D.W. 'A 200 MHz 64-b dual-issue CMOS microprocessor', IEEEJ. Solid-State Circuits. 1992, 27, (11), pp. 1555-1567
11. LU, S.L. and ERCEGOVAC, M. 'A novel implementation of double-edae-trigcered flip-flops', IEEE J. Solid-State Circuits, 1990, 25, (4), pp. 1008-1010
12. WANG, J.-S. 'A true single-phase-clocked double-cdge-triggered flipflop for low-power VLSI designs'. Proceedings of IEEE international symposium on Circuits and systems (ISCAS'97), 1997, pp. 1896-1899
13. ROGENMOSER, R. The design of high-speed dynamic CMOS circuits for VLSI' (Hartung-Gorre Verlag Konstanz, 1996)