Fault-Tolerance in Nanocomputers: A Cellular Array Approach

IEEE Transactions on Nanotechnology

Volumn 3, Issue 1 SPEC. ISS., 2004, Pages 187-201

  Peper, Ferdinand ^a   Lee, Jia ^a   Abo, Fukutaro ^b   Isokawa, Teijiro ^b   Adachi, Susumu ^a   Matsui, Nobuyuki ^b   Mashiko, Shinro ^a  

^a NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY   (Japan)

^b UNIVERSITY OF HYOGO   (Japan)

Author keywords

Cellular array; Computer architecture; Error correction; Fault tolerance; Homogeneous structure; Nanocomputing

Indexed keywords

CELLULAR ARRAYS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ERROR ANALYSIS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; MULTIPLEXING; PROBABILITY; PRODUCT DESIGN; ROBUSTNESS (CONTROL SYSTEMS);

FAULT-TOLERANCES; HOMOGENEOUS STRUCTURES; NANOCOMPUTERS; NANOCOMPUTING;

NANOTECHNOLOGY;

EID: 2342655717     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.824034     Document Type: Conference Paper

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