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Volumn 9, Issue 2 PART 3, 1999, Pages 4040-4045

Self-timed parallel adders based on di rsfq primitives

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA TRANSFER; INTERFACES (COMPUTER); JOSEPHSON JUNCTION DEVICES; PIPELINE PROCESSING SYSTEMS; ROBUSTNESS (CONTROL SYSTEMS); SPEED;

EID: 0032691717     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783914     Document Type: Article
Times cited : (9)

References (10)
  • 9
    • 33747660277 scopus 로고    scopus 로고
    • 64-bit carry-look-ahead adder based on data-driven dual-rail boolean gates, Tech. Rep. 06, HTMT RSFQ System Group, SUNY at Stony Brook, Jun. 1998 (unpublished).
    • S. Polonsky, "Performance analysis of 64-bit carry-look-ahead adder based on data-driven dual-rail boolean gates, Tech. Rep. 06, HTMT RSFQ System Group, SUNY at Stony Brook, Jun. 1998 (unpublished).
    • "Performance Analysis of
    • Polonsky, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.