Minimum dynamic power CMOS circuit design by a reduced constraint set linear program

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 527-532

  Raja, Tezaswi ^a   Agrawal, Vishwani D ^b   Bushnell, Michael L ^a  

^a RUTGERS UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

Books; Circuit simulation; Circuit synthesis; Delay; Design optimization; Energy consumption; Fans; Filtering; Hazards; Space vector pulse width modulation

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; FANS; FILTRATION; HAZARDS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; LINEAR PROGRAMMING; MODULATION; PULSE WIDTH MODULATION; SYSTEMS ANALYSIS; VECTOR SPACES; VOLTAGE CONTROL;

BOOKS; CIRCUIT SYNTHESIS; DELAY; DESIGN OPTIMIZATION; SPACE VECTOR PULSE WIDTH MODULATION;

VLSI CIRCUITS;

EID: 2342493285     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183188     Document Type: Conference Paper

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