Gate sizing in MOS digital circuits with linear programming

Proceedings of the European Design Automation Conference, EDAC 1990

Volumn , Issue , 1990, Pages 217-221

  Berkelaar, Michel R C M ^a   Jess, Jochen A G ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; GATES (TRANSISTOR); LINEAR NETWORKS; LINEAR PROGRAMMING; TIMING CIRCUITS;

DELAY MODELING; GATE SIZING; GLOBAL OPTIMUM; LINEAR PROGRAMS; OPTIMIZATION PROBLEMS; SIMPLEX ALGORITHM;

DELAY CIRCUITS;

EID: 84962312902     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAC.1990.136648     Document Type: Conference Paper

References (11)

1. FIS-85 Fishburn, J.P. and Dunlop, A.E., "TILOS: A Posy-nomial Programming Approach to Transistor Sizing", Proceedings of the IEEE International Conference on Computer Aided Design 1985, pp 326-328.
2. GLA-84 Glasser, L.A. and Hoyte L.P.J., "Delay and Power Optimization in VLSI Circuits", Proceedings of the IEEE Design Automation Conference 1984, pp 529-535.
3. HED-84 Hedlund, K.S., "Models and Algorithms for Transistor Sizing in MOS Circuits", Proceedings of the IEEE International Conference on Computer Aided Design 1984, pp 12-14.
4. KAO-84 Kao, W.H., "ARIES, a Workstation Based, Schematic Driven System for Circuit Design", Proceedings of the IEEE Design Automation Conference 1984, pp 301-307.
5. KAO-85 Kao, W.H., "Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits", Proceedings of the IEEE Design Automation Conference 1985, pp 781-784.
6. MAR-89 Marple, D., "Transistor Size Optimization in the Tailor Layout System", Proceedings of the IEEE Design Automation Conference 1989, pp 43-48.
7. MAT-85 Matson, M.D., "Optimization of Digital MOS VLSI Circuits", Proceedings of me Chapel Hill Conference on VLSI, 1985, pp 109-126.
8. ORC-68 Orchard-Hays W., "Advanced Linear Programming Computing Techniques", McGraw-Hill 1968.
9. RUE-76 Ruehli, A.U., Wolff P.K. and Goertzel G., "Power and Timing Optimization of Large Digital Systems", Proceedings of the IEEE International Symposium on Circuits And Systems 1976, pp 402-405.
10. SHY-88 Shyu, J., Sangiovanni-Vincentelli, A., Fishburn, J.P. and Dunlop, A.E., "Optimization-Based Transistor Sizing", IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, April 1988, pp 400-409.
11. SIN-88 Singh K.J., Wang A.R., Brayton R.K., Sangiovanni-Vincentelli A., "Timing Optimization of Combinational Logic", Proceedings of the IEEE International Conference on Computer-Aided Design 1988, pp 282-285.