Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Wroblewski, Artur ^a   Schimpfle, Christian V ^a   Nossek, Josef A ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SWITCHING CIRCUITS; SYNCHRONIZATION; TRANSISTORS;

SOFTWARE PACKAGE GLIMATS;

CMOS INTEGRATED CIRCUITS;

EID: 0033699048     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856054     Document Type: Conference Paper

References (8)