Timing verification and the timing analysis program

Proceedings - Design Automation Conference

Volumn Part F130197, Issue , 1988, Pages 446-456

  Hitchcock, Robert B ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; DIGITAL COMPUTERS; TIMING CIRCUITS;

PRIMARY OUTPUTS; STANDARD DEVIATION; STATISTICAL TIMING; STORAGE ELEMENTS; TEST PATTERN GENERATOR; TIMING ANALYSIS; TIMING VERIFICATION; TRADITIONAL SIMULATORS;

SOFTWARE TESTING;

EID: 84866594981     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/62882.62936     Document Type: Conference Paper

References (12)

1. B. J. Agule, J. D. Lesser, A. E. Ruehli, and P. K. Wolff, Sr., "An Experimental System for Power/Timing Optimization of LSI Chips," Proceedings of the 14th Design Automation Conference, New Orleans, (pp 147-152), 1977.
2. W. E. Donath and R. B. Hitchcock, Sr., "Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks," U.S. Patent No. 4, 263, 651, April 1981.
3. R. B. Hitchcock, G. L. Smith, and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, No. 1, (pp 100-105) 1982.
4. R. B. Hitchcock, B. L. Keller, E. Kellerman, J. F. Schroeder, and A. M. Stankosky, "Timing Analysis Results Analyzer", IBM Technical Disclosure Bulletin, Vol. 24, No. 8, (p 4229), 1982.
5. R. Kamikawai, M. Yamada, T. Chiba, K. Furumaya and Y. Tsuchiya, "A Critical Path Delay Check System," Proceedings of the 18th Design Automation Conference, Opryland, (pp 118-123), 1981.
6. T. I. Kirkpatrick and N. R. Clark, "PERT as an Aid to Logic Design," IBM Journal of Research and Development, Vol 10, No. 2, (pp 135-141), March 1966.
7. T. M. McWilliams and L. C. Widdoes Jr., "SCALD: Structured Computer-Aided Logic Design," Proceedings of the 15th Design Automation Conference, Las Vegas, (pp 271-277), 1978.
8. T. M. McWilliams, "Verification of Timing Constraints on Large Digital Systems," Proceedings of the 17th Design Automation Conference, Minneapolis, (pp 139-147), 1980.
9. D. J. Pilling, and H. B. Sun, "Computer - Aided Prediction of Delays in LSI Logic Systems," Proceedings of the 10th ACM/IEEE Design Automation Workshop, Portland, Oregon (pp 182-186), 1973.
10. A. E. Ruehli, P. K. Wolff, Sr., and G. Goertzel, "Analytical Power/Timing Optimization Technique for Digital Systems," Proceedings of the 14th Design Automation Conference, New Orleans, (pp 142-146), 1977.
11. T. Sasaki, A. Yamada, T. Aoyama, K Hasegawa, S. Kato and S. Sato, "Hierarchical Design Verification for Large Digital Systems," Proceedings of the 18th design Automation Conference, Nashville, (pp 105-112), 1981.
12. M. A. Wold, "Design Verification and Performance Analysis, Proceedings of the 15th Design Automation Conference, Las Vegas, (pp 264-270), 1978.