ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1994, Pages 61-64

  Dutta, Santanu ^a   Nag, Sudip ^a   Roy, Kaushik ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; CRITICAL PATH ANALYSIS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; SWITCHING NETWORKS; TRANSISTORS; VLSI CIRCUITS;

AUTOMATED TRANSISTOR SIZING TOOL;

INTEGRATED CIRCUIT LAYOUT;

EID: 0028602172     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)