-
3
-
-
0033722744
-
Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
-
June
-
L.A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. 27th Annual International Symposium on Computer Architecture, pages 282-293, June 2000.
-
(2000)
27th Annual International Symposium on Computer Architecture
, pp. 282-293
-
-
Barroso, L.A.1
Gharachorloo, K.2
McNamara, R.3
Nowatzyk, A.4
Qadeer, S.5
Sano, B.6
Smith, S.7
Stets, R.8
Verghese, B.9
-
5
-
-
0030348712
-
AlphaServer 4100 Performance Characterization
-
Z. Cvetanovic and D. Donaldson. AlphaServer 4100 Performance Characterization. Digital Technical Journal, 8(4), pages 3-20, 1996.
-
(1996)
Digital Technical Journal
, vol.8
, Issue.4
, pp. 3-20
-
-
Cvetanovic, Z.1
Donaldson, D.2
-
6
-
-
0029666639
-
Evaluation of multithreaded uniprocessors for commercial application environments
-
May
-
R. J. Eickemeyer, R. E. Johnson, S. R. Kunkel, M. S. Squillante, and S. Liu. Evaluation of multithreaded uniprocessors for commercial application environments. 23rd Annual International Symposium on Computer Architecture, pages 203-212, May 1996.
-
(1996)
23rd Annual International Symposium on Computer Architecture
, pp. 203-212
-
-
Eickemeyer, R.J.1
Johnson, R.E.2
Kunkel, S.R.3
Squillante, M.S.4
Liu, S.5
-
7
-
-
0031594019
-
Performance Characterization of the Quad Pentium Pro SMP Using OLTP Workloads
-
June
-
K. Keeton, D. A. Patterson, Y. Q. He, R. C. Raphael, and W. E. Baker. Performance Characterization of the Quad Pentium Pro SMP Using OLTP Workloads. 25th Annual International Symposium on Computer Architecture, pages 15-26, June 1998.
-
(1998)
25th Annual International Symposium on Computer Architecture
, pp. 15-26
-
-
Keeton, K.1
Patterson, D.A.2
He, Y.Q.3
Raphael, R.C.4
Baker, W.E.5
-
8
-
-
0031594020
-
An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors
-
June
-
J. Lo, L. A. Barroso, S. Eggers, K. Gharachorloo, H. Levy, and S. Parekh. An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. 25th Annual International Symposium on Computer Architecture, June 1998.
-
(1998)
25th Annual International Symposium on Computer Architecture
-
-
Lo, J.1
Barroso, L.A.2
Eggers, S.3
Gharachorloo, K.4
Levy, H.5
Parekh, S.6
-
11
-
-
0034442640
-
Timestamp Snooping: An Approach for Extending SMPs
-
November
-
M. Martin, D. Sorin, A. Ailamaki, A. Alameldeen, R. Dickson, C. Mauer, K. Moore, M. Plakal, M. Hill, D. Wood. Timestamp Snooping: An Approach for Extending SMPs. 9th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 25-36, November 2000.
-
(2000)
9th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 25-36
-
-
Martin, M.1
Sorin, D.2
Ailamaki, A.3
Alameldeen, A.4
Dickson, R.5
Mauer, C.6
Moore, K.7
Plakal, M.8
Hill, M.9
Wood, D.10
-
12
-
-
0034440975
-
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design
-
November
-
A. Nanda, K. Mak, K. Sugavanam, R. Sahoo, V. Soundararajan, and T. Smith. MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. 9th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 37-48, November 2000.
-
(2000)
9th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 37-48
-
-
Nanda, A.1
Mak, K.2
Sugavanam, K.3
Sahoo, R.4
Soundararajan, V.5
Smith, T.6
-
14
-
-
0031611717
-
Performance of Database Workloads on Shared- Memory Systems with Out-of-Order Processors
-
October
-
P. Ranganathan, K. Gharachorloo, S. Adve, and L. A. Barroso. Performance of Database Workloads on Shared- Memory Systems with Out-of-Order Processors. 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VIII), pages 307-318, October 1998.
-
(1998)
8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VIII)
, pp. 307-318
-
-
Ranganathan, P.1
Gharachorloo, K.2
Adve, S.3
Barroso, L.A.4
-
15
-
-
0034838875
-
Code Layout Optimizations for Transaction Processing Workloads
-
June
-
A. Ramirez, L.A. Barroso, K. Gharachorloo, R. Cohn, J. Larriba-Pey, P.G. Lowney, and M. Valero. Code Layout Optimizations for Transaction Processing Workloads. 28th Annual International Symposium on Computer Architecture, pages 155-166, June, 2001.
-
(2001)
28th Annual International Symposium on Computer Architecture
, pp. 155-166
-
-
Ramirez, A.1
Barroso, L.A.2
Gharachorloo, K.3
Cohn, R.4
Larriba-Pey, J.5
Lowney, P.G.6
Valero, M.7
-
16
-
-
84883540577
-
The impact of architectural trends on operating system performance
-
December
-
M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, and A. Gupta. The impact of architectural trends on operating system performance. 15th ACM Symposium on Operating System Principles, December 1995.
-
(1995)
15th ACM Symposium on Operating System Principles
-
-
Rosenblum, M.1
Bugnion, E.2
Herrod, S.A.3
Witchel, E.4
Gupta, A.5
-
17
-
-
0030653560
-
Using the SimOS machine simulator to study complex computer systems
-
January
-
M. Rosenblum, E. Bugnion, S. Herrod, and Scott Devine. Using the SimOS machine simulator to study complex computer systems. ACM Transactions on Modeling and Computer Simulation, Vol 7, No. 1, pages 78-103, January 1997.
-
(1997)
ACM Transactions on Modeling and Computer Simulation
, vol.7
, Issue.1
, pp. 78-103
-
-
Rosenblum, M.1
Bugnion, E.2
Herrod, S.3
Devine, S.4
-
19
-
-
84962839897
-
-
web site
-
Transaction Processing Performance Council web site. http://www.tpc.org.
-
-
-
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