A 5-GHz fully integrated BSD-protected low-noise amplifier in 90-nm RF CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 7, 2005, Pages 1434-1440

  Linien, Dimitri ^a,b,c   Thijs, Steven ^a,c   Natarajan, Mahadeva Iyer ^a   Wambacq, Piet ^a,b   Jeamsaksiri, Wutthinan ^c   Ramos, Javier ^c   Mercha, Abdelkarim ^c   Jenei, Snezana ^a,d   Donnay, Stéphane ^c   Decoutere, Stefaan ^c  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c IWT ^*

^d American Semiconductors   (Belgium)

Author keywords

CMOS; Electrostatic discharges (ESD); Low noise amplifier; Radio frequency

Indexed keywords

ELECTROSTATIC DISCHARGE (ESD); GATE OXIDES; LOW NOISE AMPLIFIERS; RADIO FREQUENCIES;

AMPLIFIERS (ELECTRONIC); CAPACITANCE; ELECTRIC POTENTIAL; ELECTRONIC EQUIPMENT; ELECTROSTATICS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 22544431685     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.847490     Document Type: Conference Paper

References (22)

1. W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe, and S. Decoutere, "Integration of a 90 nm RF CMOS technology (200 GHz fmax-150 GHz fT NMOS) demonstrated on a 5 GHz LNA," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 100-101.
2. L. M. Franca-Neto, R. E. Bishop, and B. A. Bloechel, "A 64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method," in IEEE Int. Solid-State Conf. Dig. Tech. Papers, Feb. 2004, pp. 444-445.
3. W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linien, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe, and S. Decoutere, "Integralion of a 90 nm RF CMOS technology (200 GHz fmax-150 GHz fT NMOS) demonstrated on a 5 GHz LNA," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 100-101.
4. D. Linien, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, "Low-power 5 GHz LNA and VCO in 90 nm RF CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 372-375
5. V. Vassilev, S. Thijs, P. L. Segura, P. Leroux, P. Wambacq, G. Groeseneken, M. I. Natarajan, M. Steyaert, and H. E. Maes, "ESD-RF co-design methodology for the state of the art RF-CMOS blocks," J. Microelectron. Reliab., vol. 52, no. 2, pp. 255-268, 2004.
6. S. Hyvonen, S. Joshi, and E. Rosenbaum, "Comprehensive ESD protection for RF inputs," in Proc. EOS/ESD Symp., Jun. 2003, pp. 188-194.
7. P. Leroux and M. Steyaert, "High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection," Electron, Lett., vol. 37, no. 7, pp. 467-469, Mar. 2001.
8. P. Leroux and M. Steyaert, "A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM," in Proc Eur. Solid-State Circuits Conf., Sep. 2004, pp. 295-298.
9. M. D. Ker and C. M. Lee, "ESD protection design for Giga-Hz RF CMOS LNA with novel impedance-isolation technique," in Proc. EOS/ESD Symp., Sep. 2003, pp. 204-213.
10. B. Keppens, V. De Heyn, M. I. Natarajan, V. Vassilev, and G. Groeseneken, "Significance of the failure criterion on transmission line pulse testing," Microelectron. Reliab., vol. 42, pp. 901-907, Sep. 2002.
11. R. van Langevelde, A. J. Scholten, R. J. Havens, L. F. Tiemeijer, and D. B. M. Klaassen, "Advanced compact MOS modeling," in Proc. Eur. Solid-State Device Research Conf., Sep. 2001, pp. 81-88.
12. D. K. Shaeffer and T. H. Lee, "A 1.5-V 1.5-GHz CMOS: low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
13. J. Chen and B. Shi, "Impact of intrinsic channel resistance on noise performance of CMOS LNA," IEEE Electron Device Lett., vol. 23, no. 1, pp. 34-36, Jan. 2002.
14. "Electrostatic Discharge Sensitivity Testing-Human Body Model (HBM) Component Level," ESD Association, ANSI/BSD STM5.1-2001, 2001.
15. R. O'Connor, R. Degraeve, B. Kaczer, A. Veloso, G. Hughes, and G. Groeseneken, "Weibull slope and voltage acceleration of ultrathin (1.1-1.45 nm EOT) oxynitrides," presented at the Insulating Films on Semiconductors Conf., Barcelona, Spain, Jun. 2003, paper GS26.
16. S. Thijs, M. I. Natarajan, D. Linten, V. Vassilev, T. Daenen, A. Scholten, R. Degraeve, P. Wambacq, and G. Groeseneken, "ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS-implementation concepts, constraints and solutions," in Proc. EOS/ESD Symp., Sep. 2004, pp. 40-49.
17. R. Brederlow, W. Weber, J. Sauerer, S. Donnay, P. Wambacq, and M. Vertregt, "A mixed signal design roadmap," IEEE Design Test Comput., vol. 18, no. 6, pp. 34-46, Nov.-Dec. 2001.
18. H. W. Chiu and S. S. Lu, "A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2002, pp. 226-229.
19. E. H. Westerwick, "A 5 GHz band low noise amplifier with a 2.5 dB noise figure," in Proc. IEEE Int. Symp. VLSI Technology, Systems, and Application, Apr. 2001, pp. 224-227.
20. D. Mukherjee, J. Bhattacharjee, S. Chakaraborty, and J. Laskar, "A 5-6 GHz fully integrated CMOS LNA for a dual-band WLAN receiver," in Proc. IEEE RAWCON, Sep. 2002, pp. 213-215.
21. T. K. K. Tsang and M. El-Gamal, "Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA," in Proc. ISCAS, vol. 4, May 2002, pp. 795-798.
22. D. Linten, X. Sun, G. Carchon, W. Jeamsaksiri, A. Mercha, J. Ramos, S. Jenei, L. Aspemyr, A. J. Scholten, P. Wambacq, S. Decoutere, S. Donnay, and W. De Raedt, "A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 701-704.