Impact of intrinsic channel resistance on noise performance of CMOS LNA

IEEE Electron Device Letters

Volumn 23, Issue 1, 2002, Pages 34-36

  Chen, Jiwei ^a   Shi, Bingxue ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Channel resistance; CMOS; Low noise amplifier; Noise figure; RF

Indexed keywords

ELECTRIC RESISTANCE; OPTIMIZATION; RADIO FREQUENCY AMPLIFIERS; SPURIOUS SIGNAL NOISE; TRANSCEIVERS;

LOW NOISE AMPLIFIERS (LNA);

CMOS INTEGRATED CIRCUITS;

EID: 0036160772     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.974804     Document Type: Article

References (10)

1. Integrated circuit technology options for RFIC's - Present status and future directions
2. Impact of technology scaling on CMOS RF devices and circuits
3. A robust and physical BSIM3 nonquasistatic transient and AC small-signal model for circuit simulation
4. SPICE simulation and tradeoffs of CMOS LNA performance with source-degeneration inductor
5. Gate layout and bonding pad structure of a RF n-MOSFET for low noise performance
6. RF noise simulation for submicron MOSFET's based on hydrodynamic model
7. A 1.5-V 1.5-GHz CMOS low noise amplifier