ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS - Implementation concepts, constraints and solutions

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2004, Pages

  Thijs, S ^a   Natarajan, M I ^a   Linten, D ^a,b   Vassilev, V ^a,c   Daenen, T ^a   Scholten, Andries ^d   Degraeve, R ^a   Wambacq, P ^a,b   Groeseneken, G ^a,c  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ESD PROTECTION; ONCHIP INDUCTORS; PLUG-AND-PLAY; RF CMOS TECHNOLOGY; RF-CMOS;

AUDIO FREQUENCY AMPLIFIERS; CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; LOW NOISE AMPLIFIERS;

ELECTROSTATIC DISCHARGE;

EID: 77950850406     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2004.5272635     Document Type: Conference Paper

References (9)

1. W. Jeamsaksiri, et al., "Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA", Accepted at VLSI Symposium 2004.
2. D. Linten, et al., "Low-power 5 GHz LNA and VCO in 90 nm RF CMOS", Accepted at VLSI Symposium 2004.
3. S. Hyvonen, et al., "Comprehensive ESD protection for RF inputs", Proc. EOS/ESD Symp., pp.188-194, 2003.
4. P. Leroux, et al., "High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection", Elec. Lett., 37 (7), pp. 467-469, 2001. (Pubitemid 32395307)
5. M. D. Ker, et al., "ESD Protection Design for Giga-Hz RF CMOS LNA with Novel Impedance-Isolation Technique", Proc. EOS/ESD Symp., pp. 204-213, 2003.
6. D. Linten, et al., "Design-driven Optimisation of a 90 nm RF CMOS Process by use of Elevated Source/Drain", Proc. ESSDERC., pp 43-46, 2003.
7. D.K. Shaeffer, et al., "A 1.5V 1.5 GHz CMOS Low Noise Amplifier", IEEEJ, Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
8. R. O'Connor, et al., "Weibull Slope and Voltage Acceleration of Ultra-thin (1.1-1.45 nm EOT) Oxynitrides", Proc. INFOS, paper GS26, 2003
9. V. Vassilev, et al., "Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies", Accepted at EOS/ESD Symp. 2004.