An Efficient 2-D DCT/IDCT Core Design Using Cyclic Convolution and Adder-Based Realization

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 14, Issue 4, 2004, Pages 416-428

  Guo, Jiun In ^a   Ju, Rei Chin ^a   Chen, Jia Wei ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

Binary signed digit representation; Common subexpression sharing; Cyclic convolution; Digital IP design; Discrete cosine transform (DCT); Image compression; Inverse discrete cosine transform (IDCT); SOC design; Video compression

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; COSINE TRANSFORMS; DATA ACQUISITION; IMAGE COMPRESSION; REAL TIME SYSTEMS;

BINARY SIGNED DIGIT REPRESENTATION; COMMON SUBEXPRESSION SHARING; CYCLIC CONVOLUTION; DIGITAL IP DESIGN; DISCRETE COSINE TRANSFORM (DCT); INVERSE DISCRETE COSINE TRANSFORM (IDCT); SOC DESIGN;

SIGNAL PROCESSING;

EID: 2142694467     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2004.825542     Document Type: Article

References (27)

1. N. Ahmed, T. Natarajan, and K. R. Rao, "Discrete cosine transform," IEEE Trans. Commun., vol. COM-23, pp. 90-93, Jan. 1974.
2. A. Rosenfeld and A. C. Kak, Digital Picture Processing, 2nd ed. New York: Academic, 1982.
3. P. Pirsch, N. Demassieux, and W. Gehrke, "VLSI architectures for video compression-a survey," Proc. IEEE, vol. 83, no. 2, pp. 220-246, Feb. 1995.
4. Y. P. Lee et al., "A cost effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method," IEEE Trans. Circuits Syst. Video Technol., vol. 7, pp. 459-467, June 1997.
5. S. F. Haiso, W. R. Shiue, and J. M. Tseng, "Design and implementation off a novel linear-array DCT/IDCT processor with complexity of order log2N," IEE Proc. Visions, Images, and Signal Processing, vol. 147, no. 5, pp. 400-408, Oct. 2000.
6. K. H. Cheng, C. S. Huang, and C. P. Lin, "The design and implementation of DCT/IDCT chip with novel architecture," in Proc. ISCAS, 2000, pp. IV-741-IV-744.
7. S. F. Hsiao and J. M. Tseng, "New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-msmory VLSI implementation," IEE Proc. Visions, Images, and Signal Processing, vol. 149, no. 2, pp. 97-107, Apr. 2002.
8. N. I. Cho and S. U. Lee, "DCT algorithms for VLSI parallel implementation," IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, pp. 121-127, Jan. 1990.
9. L. W. Chang and M. C. Wu, "A unified systolic array for discrete cosine and sine transforms," IEEE Trans. Signal Processing, vol. 39, pp. 192-194, Jan. 1991.
10. J. I. Guo, C. M. Liu, and C. W. Jen, "A new array architecture for prime length discrete cosine transform," IEEE Trans. Signal Processing, vol. 41, pp. 436-442, Jan. 1993.
11. A. Madisetti and A. N. Willson, Jr., "A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 135-146, Apr. 1995.
12. S. Molloy and R. Jain, "A 110-K transistor 25-Mpkels/s configurable image transform processor unit," IEEE J. Solid-State Circuits, vol. 33, pp. 86-97, Jan. 1998.
13. H. Lim, V. Piuri, and E. E. Swartzlander, Jr., "A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms," IEEE Trans. Computers, vol. 49, pp. 1297-1309, Dec. 2000.
14. H. C. Karathanasis, "A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations," IEEE Trans. Consumer Electron., vol. 41, pp. 263-272, May 1995.
15. Y. H. Hu and Z. Wu, "An efficient CORDIC array structure for the implementation of discrete cosine transform," IEEE Trans. Signal Processing, vol. 43, pp. 331-336, Jan. 1995.
16. M. T. Sun, T. C. Chen, and A. M. Gottlieb, "VLSI implementation of a 16 × 16 discrete cosine transform," IEEE Trans. Circuits Syst. II, vol. 36, pp. 610-616, Apr. 1989.
17. J. I. Guo, C. M. Liu, and C. W. Jen, "The efficient memory-based VLSI arrays for DFT and DCT," IEEE Trans. Circuits Syst. II, vol. 39, pp. 723-733, Oct. 1992.
18. D. Slawecki and W. Li, "DCT/IDCT processor design for high data rate image coding," IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 135-146, Apr. 1992.
19. D. W. Kim et al., "A compatible DCT/IDCT architecture using hardwired distributed arithmetic," in Proc. ISCAS, 2001, pp. II-457-II-460.
20. T. S. Chang, C. S. Kung, and C. W. Jen, "A simple processor core design for DCT/IDCT," IEEE Trans. Circuits Syst. Video Technol., vol. 10, pp. 439-447, Apr. 2000.
21. C.-W.Chih-Wei Hsu, W.-M.Wei-Min Chao, Y.-C.Yung-Chi Chang, and L.-G.Liang-Gee Chen, "Texture coder design of mpeg4 video by using interleaving schedule," in Proc. 2002 IEEE Int. Conf. Multimedia and Expo, vol. 2, 2002, pp. 157-160.
22. R. I. Hartley, "Sub-expression sharing in filters using canonic signed digit multipliers," IEEE Trans. Circuits Syst. II, vol. 43, pp. 677-688, Oct. 1996.
23. M. Potkonjak, M. Srivastava, and A. P. Chandrakasan, "Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common sub-expression elimination," IEEE Trans. Computer-Aided Design, vol. 15, pp. 151-165, Feb. 1996.
24. Compass, PASSPORT Library, 0.35 μm 3.3-Volt High Performance Standard Cell Library, 1996.
25. IEEE Standard Specifications for the Implementations of 8 × 8 Inverse Discrete Cosine Transform, IEEE Standard 1180-1990, Dec. 6, 1990.
26. H. R. Wu and Z. Man, "Comments on fast algorithms and implementation of 2-D discrete cosine transform," IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 128-129, Apr. 1998.
27. C. Loeffler, A. Ligtenberg, and G. S. Moschytz, "Practical fast ID DCT algorithms with 11 multiplications," in Proc. IEEE ICASSP, vol. 2, Feb. 1989, pp. 988-991.