메뉴 건너뛰기




Volumn 2, Issue , 2002, Pages 157-160

Texture coder design of MPEG4 video by using interleaving schedule

Author keywords

[No Author keywords available]

Indexed keywords

MPEG-4 VIDEO;

EID: 84908215830     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICME.2002.1035536     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 3
    • 0033720569 scopus 로고    scopus 로고
    • A scalable mpeg-4 video codec architecture for 1mt-2000 multimedia applications
    • May
    • M. Takahashi et at., "A Scalable MPEG-4 Video Codec Architecture for 1MT-2000 Multimedia Applications, " Proc. IEEE mt. Symp. Cir. Syst. (ISCAS), May 2000.
    • (2000) Proc IEEE Mt. Symp. Cir. Syst. (ISCAS)
    • Takahashi Et At, M.1
  • 5
    • 0029292227 scopus 로고
    • A 100 MHz 2-D 8x8DCT/IDCT processor for HDTV applications
    • Apr
    • A. Madisetti and A.N. Willson, "A 100 MHz 2-D 8x8DCT/IDCT processor for HDTV applications, " IEEE Trans. Cir. Syst. Video Technol., Vol. 5, No. 2, pp. 158-165, Apr. 1995.
    • (1995) IEEE Trans. Cir. Syst. Video Technol , vol.5 , Issue.2 , pp. 158-165
    • Madisetti, A.1    Willson, A.N.2
  • 6
    • 0032646532 scopus 로고    scopus 로고
    • A block processing unit in a single-chip mpeg-2 video encoder lsi
    • Y. KATAYAMA, T. KITSUKI, Y. OOI, "A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI, " Journal of VLSI Signal Processing 22, pp. 59-64, 1999.
    • (1999) Journal of VLSI Signal Processing , vol.22 , pp. 59-64
    • Katayama, Y.1    Kitsuki, T.2    Ooi, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.