A compatible DCT/IDCT architecture using hardwired distributed arithmetic

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 2, Issue , 2001, Pages 457-460

  Kim, Dae Won ^a   Kwon, Taek Won ^a   Seo, Jung Min ^a   Yu, Jae Kun ^a   Lee, Suk Kyu ^a   Suk, Jung Hee ^a   Choi, Jun Rim ^a  

^a Kyungpook National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DCT/IDCT ARCHITECTURES; DISTRIBUTED ARITHMETIC; GATE COUNT; HARDWARE IMPLEMENTATIONS; MULTI-BITS; PROCESSING ELEMENTS; TRANSPOSE MEMORY; VERILOG HDL;

HARDWARE; MATLAB; ALGORITHMS; COMPUTER SIMULATION; COSINE TRANSFORMS; DIGITAL SIGNAL PROCESSING; IMAGE CODING; MATRIX ALGEBRA;

FILTER BANKS; IMAGE COMPRESSION;

DISCRETE COSINE TRANSFORMS (DCT); DISTRIBUTED ARITHMETIC (DA);

EID: 0034998844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921106     Document Type: Conference Paper

References (9)

1. K. Rao and P. Yip, Discrete Cosine Transform. Academic press, 1990.
2. H. Sorensen and C. Burrus, "Efficient Computaion of DFT with only a subset of input or output pointa", IEEE Trans, on Signal Proc, 1993.
3. Stanley Awhite", Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review'" IEEE ASSP Magazine, July. 1989
4. A. Hossen and U. Heute, "Fast approximation DCT: Basic I, error analysis, application", IEEE Trans. On Circ. And Sys. For Video Tech., 1996.
5. J. R Choi, "A 400 Mpixels/sec IDCT for HDTV by Multibit Coding and Group Symmetry", IEEE International Solid State Circuits Conference, San Francisco, Feb. 1997
6. H. Sam, and A. Gupta, "A generalized Multibit Coding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementation", IEEE Trans. Computers, vol. 39, no. 8, Aug. 1990.
7. A. D. Booth, "A Signed Binary Multiplication Technique", Auarterly J. Mechan. Appl. Math., vol. IV, part2, 1951.
8. IEEE Std 1180-1990 "IEEE Standard Specifications for the Implementations of 8x1? Inverse Discrete Cosine Transform" Dec. 6, 1990.
9. M, R Santoro, M, A. Horowitz, "SPIM: A Pipelined 64×64-bit Iterative Multiplier", IEEE Journal of Solid State Circuits, vol. 24, No. 2, Apr. 1989