메뉴 건너뛰기




Volumn 40, Issue 6, 2005, Pages 1331-1340

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

Author keywords

Ac coupled bus; Chip to chip communication; I O interface; Multipoint bus; Pulsed signaling; Transceiver

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; INTERSYMBOL INTERFERENCE; MIM DEVICES; PRINTED CIRCUIT BOARDS; SIGNALING; TRANSFER FUNCTIONS;

EID: 20444492457     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848030     Document Type: Article
Times cited : (11)

References (17)
  • 4
    • 0034316439 scopus 로고    scopus 로고
    • Low-power area-efficient high-speed I/O circuit techniques
    • Nov.
    • M. E. Lee, W. J. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1591-1599, Nov. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , Issue.11 , pp. 1591-1599
    • Lee, M.E.1    Dally, W.J.2    Chiang, P.3
  • 7
    • 0036474723 scopus 로고    scopus 로고
    • A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme
    • Feb.
    • J. Sim, J. Nam, Y. Sohn, H. Park, C. Kim, and S. Cho, "A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 245-250, Feb. 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , Issue.2 , pp. 245-250
    • Sim, J.1    Nam, J.2    Sohn, Y.3    Park, H.4    Kim, C.5    Cho, S.6
  • 13
    • 0031104164 scopus 로고    scopus 로고
    • Capacitive coupling and quantized feedback applied to conventional CMOS technology
    • Mar.
    • T. J. Gabara and W. C. Fischer, "Capacitive coupling and quantized feedback applied to conventional CMOS technology," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 419-427, Mar. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , Issue.3 , pp. 419-427
    • Gabara, T.J.1    Fischer, W.C.2
  • 14
    • 0242443732 scopus 로고    scopus 로고
    • A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multichip access and reconfigurable I/O capability
    • Sep.
    • J. Kim, Z. Xu, and M. F. Chang, "A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multichip access and reconfigurable I/O capability," in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2003, pp. 317-321.
    • (2003) Proc. IEEE Custom Integrated Circuits Conf. , pp. 317-321
    • Kim, J.1    Xu, Z.2    Chang, M.F.3
  • 15
    • 0032625917 scopus 로고    scopus 로고
    • Two high-bandwidth memory bus structures
    • Jan.-Mar.
    • B. Millar and P. Gillingham, "Two high-bandwidth memory bus structures," IEEE Des. Test Comput., vol. 16, no. 1, pp. 42-52, Jan.-Mar. 1999.
    • (1999) IEEE Des. Test Comput. , vol.16 , Issue.1 , pp. 42-52
    • Millar, B.1    Gillingham, P.2
  • 17
    • 2942691843 scopus 로고    scopus 로고
    • A 1.8-V 700 Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration
    • Jun.
    • C. Yoo, K. Kyung, K. Lim, H. Lee, J. Chai, N. Heo, D. Lee, and C. Kim, "A 1.8-V 700 Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 941-951, Jun. 2004.
    • (2004) IEEE J. Solid-state Circuits , vol.39 , Issue.6 , pp. 941-951
    • Yoo, C.1    Kyung, K.2    Lim, K.3    Lee, H.4    Chai, J.5    Heo, N.6    Lee, D.7    Kim, C.8


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.