Two high-bandwidth memory bus structures

IEEE Design and Test of Computers

Volumn 16, Issue 1, 1999, Pages 42-52

  Millar, Bruce ^a,b,c   Gillingham, Peter ^a,b,c  

^a MOSAID Technologies   (Canada)

^b IEEE   (Canada)

^c MOSAID Technologies Inc   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PACKET NETWORKS;

MEMORY BUS STRUCTURES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032625917     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.748804     Document Type: Article

References (11)

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