A low power capacitive coupled bus interface based on pulsed signaling

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 35-38

  Kim, Jongsun ^a   Choi, Jung Hwan ^b   Kim, Chang Hyun ^b   Chang, M Frank ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLED BUS INTERFACE; CHANNEL TERMINAL; METAL-INSULATOR-METAL (MIM) CAPACITORS; PULSED SIGNALING;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; PRINTED CIRCUIT BOARDS; SIGNAL TO NOISE RATIO; SIGNALING; SYNCHRONOUS MACHINERY;

MICROPROCESSOR CHIPS;

EID: 17044407847     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Thaddeus J. Gabara, Wilhelm C. Fischer, "Capacitive Coupling and Quantized Feedback Applied to Conventional CMOS Technology," IEEE J. Solid-State Circuits, pp.419-427, March 1997.
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3. Robert J. Drost, et al., "Proximity Communication," IEEE Custom Integrated Circuits Conference, pp.469-472, Sep. 2003.
4. K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, T. Sakurai, "1.27Gb/s/pin 3mW/pin Wireless Superconnect (WSC) Interface Scheme," ISSCC Digest of Technical Papers, pp.186-187, Feb. 2003.
5. Jared L. Zerbe, et al., "1.6 Gb/s/pin 4-PAM Signaling and Circuits for a Multidrop Bus," IEEE J. Solid-State Circuits, pp.752-760, May 2001.
6. Bruce M, Peter G, "Two High-Bandwidth Memory Bus Structures," Design and Test of Computers, IEEE, Vol. 16, pp.42-52, Jan.-March 1999.