-
2
-
-
0013158154
-
Architecture and CAD for Speed and Area Optimization of FPGAs
-
V. Betz, "Architecture and CAD for Speed and Area Optimization of FPGAs," Ph. D. Dissertation, University of Toronto, 1998
-
(1998)
Ph. D. Dissertation, University of Toronto
-
-
Betz, V.1
-
4
-
-
84949800774
-
Routability-Driven Packing for Cluster-Based FPGAs
-
Yokohama, Japan
-
E. Bozorgzadeh, S. Ogrenci and M. Sarrafzadeh, "Routability-Driven Packing for Cluster-Based FPGAs," ASPDAC, Yokohama, Japan, 2001
-
(2001)
ASPDAC
-
-
Bozorgzadeh, E.1
Ogrenci, S.2
Sarrafzadeh, M.3
-
6
-
-
0034477815
-
Multilevel Optimization for Large-scale Circuit Placement
-
San Jose, California, November
-
T. Chan, J. Cong, T. Kong and J. Shinnerl, "Multilevel Optimization for Large-scale Circuit Placement," Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 171-176, November 2000
-
(2000)
Proc. IEEE International Conference on Computer Aided Design
, pp. 171-176
-
-
Chan, T.1
Cong, J.2
Kong, T.3
Shinnerl, J.4
-
7
-
-
0037387778
-
Multilevel Global Placement with Congestion Control
-
July
-
C.-C. Chang, J. Cong, D. Pan, and X. Yuan, "Multilevel Global Placement with Congestion Control," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp. 395-409, July 2002
-
(2002)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.22
, Issue.4
, pp. 395-409
-
-
Chang, C.-C.1
Cong, J.2
Pan, D.3
Yuan, X.4
-
9
-
-
0028259317
-
FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs
-
January
-
J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design, vol. 13, no. 1, pp. 1-12, January 1994
-
(1994)
IEEE Trans. on Computer-Aided Design
, vol.13
, Issue.1
, pp. 1-12
-
-
Cong, J.1
Ding, Y.2
-
10
-
-
0032642353
-
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
-
New Orleans, Louisiana, June
-
J. Cong, H. Li and C. Wu "Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization," Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 460-465, June 1999
-
(1999)
Proc. 36th ACM/IEEE Design Automation Conf.
, pp. 460-465
-
-
Cong, J.1
Li, H.2
Wu, C.3
-
14
-
-
26444479778
-
Optimization by Simulated Annealing
-
May 13
-
S.S. Kirkpatrick, C. Gelatt and M. Vecchi, "Optimization by Simulated Annealing," Science, pp. 671-680, May 13, 1983
-
(1983)
Science
, pp. 671-680
-
-
Kirkpatrick, S.S.1
Gelatt, C.2
Vecchi, M.3
-
15
-
-
0026131224
-
GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization
-
J.M. Kleinhans, G. Sigl, F.M. Johannes and K.J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10:356-365, 1991
-
(1991)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.10
, pp. 356-365
-
-
Kleinhans, J.M.1
Sigl, G.2
Johannes, F.M.3
Antreich, K.J.4
-
17
-
-
0032659075
-
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
-
Monterey, CA
-
A. Marquardt, V. Betz and J. Rose, "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 37-46, 1999
-
(1999)
ACM/SIGDA International Symposium on Field Programmable Gate Arrays
, pp. 37-46
-
-
Marquardt, A.1
Betz, V.2
Rose, J.3
-
18
-
-
0033723218
-
Timing-Driven Placement for FPGAs
-
Monterey, CA, February
-
A. Marquardt, V. Betz and J. Rose, "Timing-Driven Placement for FPGAs," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 203-213, February 2000
-
(2000)
ACM/SIGDA International Symposium on Field Programmable Gate Arrays
, pp. 203-213
-
-
Marquardt, A.1
Betz, V.2
Rose, J.3
-
19
-
-
0013384346
-
SIS: A System for Sequential Circuit Synthesis
-
Memorandum No. UCB/ERL M92/41
-
E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, 1992
-
(1992)
Electronics Research Laboratory
-
-
Sentovich, E.1
Singh, K.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.8
Brayton, R.9
Sangiovanni-Vincentelli, A.10
-
23
-
-
0034474792
-
Effective Partitioning-Driven Placement with Simultaneous Level Processing and Global Net Views
-
San Jose, California, November
-
K. Zhong and S. Dutt, "Effective Partitioning-Driven Placement with Simultaneous Level Processing and Global Net Views," Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 254-259, November 2000
-
(2000)
Proc. IEEE International Conference on Computer Aided Design
, pp. 254-259
-
-
Zhong, K.1
Dutt, S.2
|