Cell replication and redundancy elimination during placement for cycle time optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 25-30

  Neumann, Ingmar ^a   Stoffel, Dominik ^a   Hartje, Hendrik ^a   Kunz, Wolfgang ^a  

^a GOETHE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; OPTIMIZATION; TRANSISTORS;

AUTOMATIC TEST PATTERN GENERATION; CELL REPLICATION; CELL REPLICATION ALGORITHMS; CYCLE TIME OPTIMIZATION; STUCK AT FAULT TESTABILITY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033338598     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)