Performance and new effects in advanced SOI devices and materials

Microelectronic Engineering

Volumn 80, Issue SUPPL., 2005, Pages 230-240

  Balestra, Francis ^a   Jomaah, Jalal ^a  

^a IMEP LAHC   (France)

Author keywords

Memories; Multi gates; Physical mechanisms; SOI; Strained layers

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ELECTRON TUNNELING; GATES (TRANSISTOR); IMPACT IONIZATION; INTERFACES (MATERIALS); LEAKAGE CURRENTS; SILICON; STRAIN RATE; THIN FILMS; THRESHOLD VOLTAGE;

MULTI-GATES; PHYSICAL MECHANICS; SPECTRAL DENSITY; STRAINED LAYERS; THERMAL FLOATING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 19944399422     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.069     Document Type: Conference Paper

References (32)

1. J.P. Colinge Silicon-On-Insulator technology: materials to VLSI 1991 Kluwer Academic Publishers
2. S. Cristoloveanu, and S.S. Li Electrical characterization of Silicon-On-Insulator materials and devices 1995 Kluwer Academic Publishers
3. F. Balestra, SOI devices, Wiley Encyclopedia of Electrical and Electronics Engineering, 1999.
4. F. Dieudonné et al, Gate-induced floating body effect, low frequency noise and hot carrier reliability in advanced SOI MOSFETs, Solid-St. Electron., in press.
5. E. Simoen et al, Electron valence-band tunneling excess noise in twin-gate silicon-on-insulator MOSFETs, Proc. ULIS'2005, Bologna, April 2005.
6. W. Xiong et al, Full/partial depletion effects in FinFETs, Proc. IEEE Intern. SOI Conf., p. 195, 2004.
7. L. Zafari et al, On the low frequency noise in fully depleted and double-gate SOI transistors, Proc. ULIS'2005, Bologna, April 2005.
8. N. Bresson et al, Alternative dielectrics for advanced SOI MOSFETs: thermal properties and short channel effects, Proc. IEEE Intern. SOI Conf., p. 62, 2004.
9. E. Pop et al, Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs, Proc. IEDM'2004, p. 411.
10. D.P. Ioannou et al, New insights on the hot-carrier characteristics of 55nm PD SOI MOSFETs, Proc. IEEE Intern. SOI Conf., p. 205, 2004.
11. J.J. Lee et al, Mobility enhancement of SSOI devices fabricated with sacrificial thin relaxed SiGe, Proc. IEEE Intern. SOI Conf., p. 139, 2004.
12. M. Sadaka et al, Fabrication and operation of sub-50nm strained-Si on Si1-xGex on insulator (SGOI) CMOSFETs, Proc. IEEE Intern. SOI Conf., p. 209, 2004.
13. T. Numata et al, Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si devices parameters, Proc. IEDM'04, p. 177.
14. J. Cai et al, Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI), Proc. IEDM'04, p. 165.
15. I. Aberg et al, High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si Heterostructures on Insulator, Proc. IEDM'2004, p. 173.
16. K. Uchida et al, Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultra-thin-body SOI MOSFETs, Proc. IEDM'2004, p. 229.
17. T. Guillaume et al, Influence of the mechanical strain induced by a metal gate on electron and hole transport in single and double-gate SOI MOSFETs, Proc. IEEE Intern. SOI Conf., p. 42, 2004.
18. H. Shang, Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS, Proc. IEDM'2004, p. 157.
19. T. Low, Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETs, Proc. IEDM'2004, p. 151.
20. E. Landgraf et al, Influence of crystal orientation and body doping on trigate transistor performance, Proc. ULIS'2005, Bologna, April 2005.
21. F. Balestra Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance IEEE Electron Dev. Lett EDL-8 1987 410
22. S. Eminente et al, Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study, Proc. IEDM'2004, p. 609.
23. M. Bescond et al, 3D quantum modeling and simulation of multiple-gate nanowire MOSFETs, Proc. IEDM'2004, p. 617.
24. J. Saint-Martin et al, Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation, Proc. ULIS'2005, Bologna, April 2005.
25. A. Khakifirooz et al, Assessing the performance limits of ultra-thin double-gate MOSFETs: Silicon vs. Germanium, Proc. IEEE Intern. SOI Conf., p. 79, 2004.
26. C. Yin et al, Characterization and edge direct tunneling leakage of gate misaligned double gate MOSFETs, Proc. IEEE Intern. SOI Conf., p. 91, 2004.
27. J. Widiez et al, Experimental gate misalignment analysis on double gate SOI MOSFETs, Proc. IEEE Intern. SOI Conf., p. 185, 2004.
28. A. Bansal et al, Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices, Proc. IEEE Intern. SOI Conf., p. 94, 2004.
29. E.-J. Yoon et al, Sub-30nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application, Proc. IEDM'2004, p. 627.
30. A. Marchi et al, Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs, Proc. ULIS'2005, Bologna, April 2005.
31. T. Tanaka et al, Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM, Proc. IEDM'2004, p. 919.
32. U. Avci et al, Back-floating gate non-volatile memory, Proc. IEEE Intern. SOI Conf., p. 133, 2004.